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Do not send an AI-generated schematic, PCB layout, FPGA design or RTL straight to fabrication. Treat the output as a proposed implementation: define measurable requirements, freeze the exact design and inputs, map every requirement to objective evidence, run the analyses and simulations appropriate to the domain, inspect interfaces and assumptions, test representative hardware where models are insufficient, close discrepancies, and obtain human engineering approval.
This is the difference between checking whether an implementation was built correctly and checking whether it is the right solution. NASA describes verification as asking whether “the end product was realized right” and validation as asking whether “the right end product was realized.” A convincing AI explanation is neither; sign-off requires reproducible evidence tied to a controlled design revision.
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What is the difference between verifying and validating an AI-generated hardware design?
Verification demonstrates that the design satisfies specified requirements. Validation demonstrates that the requirements and resulting product address the intended user, mission or operating need. A design can pass every simulation that was written for it and still be the wrong product, or satisfy a functional requirement while violating a safety, environmental or manufacturing constraint.
NASA’s Systems Engineering Handbook defines verification as a formal process using test, analysis, inspection or demonstration to confirm that a system and its hardware and software components satisfy all specified requirements. Validation is the complementary question: whether the realized product is the right one for its intended context.
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Verification asks “did we build it right?”
Examples include checking that a regulator delivers its specified voltage over load, that an interface obeys its timing limits, that an FPGA state machine reaches every required state, or that a PCB maintains required clearances. The requirement, method, configuration and pass rule must be explicit.
Validation asks “did we build the right thing?”
Validation checks operational suitability. A sensor board may meet its electrical requirements yet fail because its connector cannot be reached in the enclosure, its thermal behavior is unacceptable in the installed location, or its user workflow is unsafe. These are system-context failures that an isolated netlist or RTL simulation may not reveal.
What should be defined before checking an AI-generated design?
Start with intended use and measurable requirements. Do not let the generated artifact define its own success criteria.
State the operating context
Record who or what will use the product, where it will operate, expected duty cycle, interfaces to neighboring systems, service assumptions and consequences of failure. Include environmental and regulatory boundaries, not just nominal voltage and clock frequency.
Turn goals into verifiable requirements
Write requirements so that each can be verified by test, demonstration, inspection or analysis. “Low power” is not a usable acceptance criterion; a limit such as average and peak power under a named workload and operating range is. “Reliable communication” needs measurable throughput, latency, error-rate or recovery requirements and defined conditions.
- Functional: required operations, modes, inputs, outputs and fault responses.
- Performance: speed, accuracy, capacity, latency, power, thermal limits and timing.
- Interface: electrical levels, protocols, pin assignments, timing, reset behavior and mechanical connections.
- Environmental: temperature, humidity, vibration, shock, altitude, contamination and other applicable limits.
- Safety and regulatory: isolation, protective behavior, emissions, immunity, material or certification constraints.
- Manufacturing: tolerances, assembly rules, test access, component availability and inspection criteria.
Assign an identifier to every requirement. An identifier lets reviewers trace the requirement through design elements, evidence, anomalies and approval without relying on an AI-generated narrative.
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Freeze one exact configuration before evaluating it. Evidence is valid only for the design and inputs that produced it.
Place the schematic, PCB or mechanical CAD, RTL, constraints, bill of materials, drawings, models, calculations and scripts under version control. Record the revision identifier or immutable commit for each item. Preserve the prompts or input data that materially influenced generation, along with the AI tool, model and library versions used.
Capture analysis inputs, not just files
For every simulation or calculation, retain units, material properties, component models, loads, boundary conditions, initial conditions, tolerances, solver settings and assumptions. A thermal result without the power map and convection assumptions cannot be reproduced or assessed. A timing result without the clock constraints and process assumptions is not evidence for a different build.
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Control changes after the baseline
Use a change record for edits to the design, constraints, libraries, models, prompts or requirements. NASA product-realization guidance warns that modifications made without configuration control can create major performance problems. When a material change occurs, identify affected requirements and rerun the corresponding analyses, simulations or tests rather than treating the old result as transferable.
How do I build a verification matrix?
Create one row for every requirement and specify how it will be shown to pass. NASA identifies inspection, analysis, demonstration and test as the core verification methods.
| Field | What to record |
|---|---|
| Requirement ID and text | The controlled requirement and its revision |
| Verification method | Inspection, analysis, demonstration or test; more than one may be needed |
| Procedure or model | Test steps, instrument setup, simulation case, inspection drawing or demonstration script |
| Configuration | Design revision, hardware serial or build, software/RTL image, tool and library versions |
| Acceptance rule | Numerical limit, required behavior, visual criterion or other unambiguous pass condition |
| Result and evidence | Raw data, plots, logs, photographs, reports or signed inspection record |
| Anomalies and disposition | Failure, waiver, corrective action, retest and residual risk |
| Owner and approval | Responsible engineer, independent reviewer where appropriate and approval date |
A matrix exposes unverified requirements early. It also prevents a common AI failure mode: a polished explanation that mentions behavior without producing an objective result tied to a pass rule.
Which automated checks should an electronic or RTL design pass?
Run a layered set of checks; no single tool establishes system-level correctness. Select checks according to the technology, safety impact and failure modes.
Compile, elaborate and lint
For RTL, compile all sources with the controlled toolchain and elaborate the complete hierarchy. Resolve width, signedness, unreachable logic, inferred storage, multiple drivers and reset-related warnings according to documented policy. For schematics and PCB data, run electrical-rule checks, netlist consistency checks, design-rule checks and manufacturability checks with the exact libraries used for release.
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Check clock, reset and power intent
Use clock-domain crossing and reset-domain crossing analysis where multiple asynchronous domains exist. Review synchronization, reset release, metastability assumptions and recovery behavior. Apply low-power or power-intent checks when the design includes voltage domains, isolation, retention or power gating; verify sequencing rather than only steady-state values.
Simulate with assertions and coverage
Build directed and constrained cases for normal operation, legal transitions, invalid inputs, reset, startup and recovery. Assertions should encode safety and protocol invariants. Track functional and code coverage, but treat coverage as evidence of exercised scenarios, not proof that unmodeled behavior is impossible. A high percentage can coexist with an incomplete requirement set.
Use formal and equivalence methods where they fit
Formal property checking can explore state-space conditions that directed tests miss, while equivalence checking can show that an optimization or generated implementation preserves a reference behavior. Define assumptions explicitly; an incorrect assumption can make a formally proven result irrelevant to the real environment.
Analyze timing, power, physical and reliability behavior
Run timing analysis with controlled clocks, constraints and corners. Estimate dynamic and static power under representative activity, then check voltage drop, thermal paths and component ratings. For a PCB, include signal integrity, power integrity, electromagnetic compatibility risks, creepage and clearance, mechanical fit and component derating as applicable. For RTL, include implementation timing and resource limits after synthesis and place-and-route, not only pre-synthesis simulation.
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Make regressions reproducible
Record test seeds, input vectors, tool versions, configuration files and generated artifacts. A rerun should identify whether a result changed because the design changed, the environment changed or the test was nondeterministic.
How should assumptions and interfaces be reviewed?
Perform an independent review of the design in its operating context. AI systems often produce locally plausible blocks whose assumptions do not match neighboring hardware.
Electrical and logical interfaces
- Compare every pin, polarity, voltage level, termination and pull-up or pull-down against the receiving device.
- Check clock frequencies, phase relationships, reset assertion and release, boot sequencing and brownout behavior.
- Verify power-up current, inrush, sequencing and fault isolation against the actual supply and protection design.
- Confirm protocol limits, buffer sizing, timeout behavior, retries and behavior after corrupted or missing data.
Physical and environmental interfaces
- Check connector keying, cable bend radius, enclosure clearances, mounting, keep-outs and service access.
- Review thermal paths from heat sources through packages, copper, interfaces and the enclosure.
- Verify material data, loads, tolerances and boundary conditions used by mechanical or structural analyses.
- Check manufacturability, assembly orientation, test access, inspection visibility and the availability or lifecycle status of critical parts.
Require the reviewer to challenge each assumption: who supplied it, how current it is, what happens outside its range and which requirement depends on it. An assumption that cannot be justified should become a requirement, a measured input or an explicit risk.
Can simulation alone validate an AI-generated circuit?
No. Simulation is often necessary, but it cannot expose every failure that the model omits. ECSS verification guidance includes analysis, simulation, prototype testing, design review and inspection because each reveals different evidence.
Models simplify parasitics, manufacturing variation, component behavior, software interaction, user actions and environmental stress. An idealized regulator model may not capture control-loop instability with the selected layout. A protocol simulation may not reveal an incorrect connector pinout. A thermal model can miss a poorly bonded interface or blocked airflow.
Use analysis for what is observable in a credible model
Analysis is appropriate when governing equations, inputs and uncertainty are understood and the result can be compared with a requirement. Document model correlation, sensitivity and limitations. If a parameter is uncertain, analyze its range or measure it rather than silently choosing a favorable value.
Escalate when the model cannot establish behavior
Use a representative prototype, breadboard, engineering model or hardware-in-the-loop setup when interfaces, physical effects, human operation or fault behavior are not credibly modeled. The prototype should preserve the features that drive the risk; a convenient demo board is not evidence for a different power tree, enclosure, connector or clock architecture.
What do inspection, demonstration and testing each prove?
Choose the method that observes the required fact directly and use more than one when risk warrants it.
| Method | Best for | Typical evidence | Important limitation |
|---|---|---|---|
| Inspection | Observable construction, identity, workmanship and configuration | Drawings, photographs, measurements, labels, assembly records and signed checklists | It cannot establish internal behavior under operating load. |
| Analysis | Modeled electrical, thermal, structural, timing or reliability behavior | Controlled inputs, calculations, simulation outputs, margins and sensitivity results | Its validity depends on model fidelity and assumptions. |
| Demonstration | Operational tasks or user-visible capabilities | Procedure, setup, observed actions, outputs and acceptance record | It may not quantify stresses or worst-case limits. |
| Test | Measured behavior of representative hardware or an integrated system | Instrument calibration, configuration, raw data, plots, anomalies and retest results | One build and one condition do not automatically represent every production unit or environment. |
Inspection can establish that a connector, clearance or marking exists. Demonstration can show that a device boots and performs a user task. Test can measure behavior under specified loads. Analysis can cover conditions that are expensive or destructive to reproduce. The matrix should state why the chosen method is sufficient for that requirement.
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How should margins and off-nominal cases be exercised?
Test the conditions that could invalidate assumptions, not only the nominal happy path. NASA describes qualification testing at environmental extremes to establish margins, with acceptance testing used on produced units.
Select stress cases from risk
- Electrical: minimum and maximum supply, load transients, startup, shutdown, brownout, short or open faults where safe, and tolerance stacks.
- Thermal: hot and cold operating points, warm-up, heat soak, duty-cycle extremes and thermal throttling or shutdown.
- Mechanical: vibration, shock, mounting variation, connector insertion or cable loads and enclosure tolerances.
- EMC and signal integrity: susceptibility, emissions, long-cable behavior, simultaneous switching and degraded signal conditions as applicable.
- Digital faults: invalid packets, clock loss, reset during traffic, memory corruption, stuck-at conditions, arbitration conflicts and recovery time.
- Endurance: repeated power cycles, long-duration operation, write or erase cycles and thermal cycling when life is a requirement.
Define the stress level, duration, sequence, instrumentation and pass rule before running the test. Qualification seeks margin and may use a dedicated representative unit; acceptance testing checks that each produced unit meets its release criteria. Do not confuse the two.
How do different validation approaches compare?
Compare approaches by the evidence they produce, not by how sophisticated the tool sounds. The least expensive combination is acceptable only when it covers every requirement with credible evidence.
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| Approach | Requirement coverage | Model or interface realism | Off-nominal and environmental coverage | Independence and reproducibility | Residual-risk treatment |
|---|---|---|---|---|---|
| Simulation and formal analysis | Strong for explicitly modeled behavior and properties | Limited by models, assumptions and testbench interfaces | Broad and repeatable if scenarios are modeled | Highly repeatable; independent review of assumptions remains necessary | Escalate unmodeled risks to inspection or hardware testing |
| Design review and inspection | Strong for configuration, construction, interfaces and workmanship | Examines the real artifact but not all dynamic behavior | Usually limited unless the inspection is performed under stress | Can be independently repeated with controlled checklists | Pair with analysis or test for behavioral claims |
| Representative prototype test | Strong for measured behaviors selected in the procedure | High for included hardware, loads and interfaces | Can cover realistic faults and environments within safe limits | Repeatability depends on setup, instrumentation and build variation | Use anomalies and margins to decide redesign, retest or escalation |
| Qualification or environmental test | Strong for requirements exercised at defined extremes | High when the unit and configuration represent the intended product | Specifically targets extremes, endurance and stress margins | Requires controlled facilities, calibration and documented configuration | Failures require disposition; passing one unit does not erase production variation |
Ask seven questions when choosing between methods: Does it cover the requirement, represent the real interfaces, include off-nominal and environmental conditions, use an independent review, reproduce results, fit the available time and resources, and leave residual risk that has been explicitly accepted? Prototype or qualification testing is warranted where analysis cannot establish behavior.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What should happen when a check fails or the design changes?
Record the discrepancy and stop treating the affected requirement as verified until the issue is resolved or formally accepted.
- Describe the observed result, expected result, configuration and exact procedure or analysis case.
- Classify the failure: design defect, test setup error, model limitation, requirement ambiguity, manufacturing issue or inconclusive evidence.
- Identify affected requirements, interfaces, analyses, drawings, prompts, libraries and downstream tests.
- Implement the correction under configuration control and review any waiver or deviation with its safety and residual-risk rationale.
- Repeat the affected evidence and any regression evidence needed to show that other requirements were not damaged.
- Update the matrix, anomaly record and release package with the new result, reviewer and approval date.
Do not “fix” a failed result by changing the acceptance limit after seeing the data unless the requirement itself is formally revised and the impact is reviewed. A changed requirement is a new verification obligation.
Who can approve an AI-assisted design for fabrication?
A qualified human engineer or accountable engineering authority must approve release. Cadence’s guidance is explicit: autonomous execution does not mean autonomous signoff.
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What a release package should contain
- Approved requirements and intended-use statement.
- Frozen schematic, PCB or CAD, RTL, constraints, BOM, drawings and manufacturing outputs.
- Tool, library, model, material, prompt and input-data versions that materially affected generation.
- Verification matrix with procedures, acceptance rules, results and objective evidence.
- Simulation, formal, timing, power, thermal, physical and reliability reports as applicable.
- Inspection, demonstration, prototype, qualification and acceptance-test records.
- Open discrepancies, approved waivers, residual-risk statement and change-control history.
- Named engineering approvals for design, safety, manufacturing and system integration where required.
AI-generated explanations can help a reviewer navigate this package, but they are not substitutes for the underlying logs, measurements, calculations or signed decisions. As Cadence puts it, “An explanation from the model is not a verification result.”
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Which standards and guidance should inform the process?
Use the standards that apply to the product’s industry, assurance level and geography; none removes the need to understand the design.
IEEE 1012-2024
IEEE 1012-2024 is an active IEEE Computer Society standard covering system, software and hardware verification and validation. It was published on August 22, 2025. Its processes can help structure lifecycle evidence, independence and reviews, but the project should determine the clauses and tailoring appropriate to its assurance needs.
IEEE P4102
IEEE P4102 is an active IEEE Standards Association project concerning AI use in electronic-system and IC development; its PAR was approved on March 26, 2026. Because it is still a project, its eventual requirements are not settled compliance criteria. Do not claim conformity to a final standard that does not yet exist.
EN 16603-20-40:2024
EN 16603-20-40:2024 is an ECSS/SIST edition addressing space engineering verification. It is relevant where the project falls within that regulated context and illustrates the value of combining analysis, simulation, prototype testing, design review and inspection. Other sectors may require different standards, environmental levels or certification authorities.
What is the minimum defensible gate before ordering prototypes?
Fabrication is defensible only when the following questions can be answered from controlled records:
- Is the intended use explicit, and does every functional, performance, interface, environmental, safety and manufacturing requirement have an acceptance rule?
- Is the exact design, BOM, RTL or CAD, toolchain, library, model, prompt and analysis input frozen and uniquely identified?
- Does the verification matrix identify an appropriate method and owner for every requirement?
- Have compilation, elaboration, lint, CDC/RDC, power-intent, simulation, assertions, formal, equivalence, coverage, timing, power, physical and reliability checks been run where applicable?
- Have an independent reviewer challenged units, pinouts, clocks, resets, power sequencing, tolerances, thermal paths, clearances, materials, loads, manufacturability and safety margins?
- Have representative hardware or other direct observations been used for behavior that the models cannot establish?
- Have margins, faults and environmental extremes been selected from the risk analysis and documented with pass rules?
- Are all discrepancies closed or formally accepted, are affected results rerun after changes, and has an accountable engineer approved release?
If any answer is “not yet,” the design may be a useful engineering candidate, but it is not ready for an uncontrolled prototype order.
Frequently Asked Questions
What records should I keep if the AI tool is updated between design revisions?
Record the model or service version, date, relevant settings, prompts or input files, generated outputs and the human changes made afterward. Treat an update that can alter generated logic, component choices or explanations as a configuration change and assess which evidence must be rerun.
Should an AI-generated PCB be reviewed differently from AI-generated RTL?
The evidence framework is the same, but the risk-specific checks differ. PCB work emphasizes libraries, footprints, clearances, power integrity, thermal paths, manufacturability and physical inspection; RTL work adds elaboration, CDC/RDC, assertions, formal properties, synthesis, implementation timing and hardware-software interaction.
How representative must a prototype be for its test results to count?
It must include the features that drive the requirement or risk: the relevant power tree, clocks, interfaces, loads, enclosure or thermal path, and intended firmware where applicable. A simplified demonstrator can answer a narrow question, but its result should not be extended to omitted features without analysis or additional testing.
When is an independent reviewer required?
Independence is most important when failure could affect safety, mission success, compliance or substantial cost, and when the designer may be biased by the generated result. The project’s assurance rules should define independence, but every review should at least identify who challenged assumptions and who accepted residual risk.
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