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Marvell’s Photonic Fabric is designed to let multiple accelerator servers access a shared memory tier over optical connections, rather than keeping all usable memory inside each GPU server. The advertised 32 TB is pooled appliance-level capacity for warm large-language-model KV cache—not 32 TB of HBM in one GPU, and not the capacity of a single memory module. The idea is to add capacity separately from compute, so reusable context can remain available to workloads without occupying scarce accelerator memory.
What does it mean to pool GPU memory with a photonic fabric?
It means separating some memory capacity from the GPU or accelerator package and making that capacity accessible to multiple hosts through a fabric. In Marvell’s design, memory modules and optical connectivity form a shared tier that can serve multiple XPUs—the broad term for AI accelerators—or GPU servers. Compute and this additional memory can therefore scale more independently.
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This does not combine several GPUs’ local HBM into one larger, uniform block of equally fast memory. Instead, it adds a further tier to the hierarchy: local HBM remains attached to each accelerator, while a Photonic Fabric Memory Module provides a larger DDR5-backed pool with an HBM cache. Optical links carry memory transactions between hosts and modules, including across racks.
Marvell describes the architecture as providing approximately less than 350 nanoseconds of near-NUMA access across multiple racks, with reach up to 50 meters. Those are vendor architecture claims, not measurements of a published, independently tested production deployment.
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What is a Photonic Fabric Memory Appliance?
It is the appliance-level system that presents a pool of memory to connected compute. Marvell’s announcement describes up to 32 TB of warm KV-cache offload at this level. The appliance is not the same thing as one module: Marvell’s module-level specifications describe a smaller building block with DDR5, an HBM cache and optical-fabric bandwidth.
What is in a module?
Marvell says a Photonic Fabric Memory Module can contain up to eight DDR5 DIMMs, a 72 GB HBM cache and 7.2 Tbps of optical-fabric bandwidth. The HBM cache sits in front of the larger DDR5 capacity. The module connects into the broader fabric through Photonic Fabric NICs and chiplets, which help connect hosts and memory modules.
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1Fix the driver behind crashes, sound loss and screen glitches2Repair Windows errors before they cause bigger problems3Scan for outdated or missing drivers - takes under a minuteThese are maximum figures stated by Marvell in 2026, not a guarantee that every appliance ships with that exact configuration. The public materials cited here do not establish the final shipping configuration or the number of modules in a 32 TB appliance.
What exactly does 32 TB mean?
It is Marvell’s stated maximum target for warm KV-cache offload across an appliance-level shared tier. The capacity can serve multiple XPUs or racks; it is not 32 TB of accelerator HBM for one GPU, nor 32 TB per module.
A separate photonic-CXL paper describes a 32 TB configuration across 16 hosts using a passive fiber shuffle and a switch-free crossbar. That is a related research architecture, not proof that Marvell’s appliance uses the same host count or topology. The two figures should not be treated as interchangeable.
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The distinction matters when estimating capacity. “32 TB” identifies a pool, but by itself does not say how much is available to a particular host at a particular moment, how the pool is partitioned among workloads, or how much memory a given model’s context will consume. The announcement establishes the intended workload and aggregate capacity, not those deployment-specific allocations.
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The architecture adds a shared tier; it does not eliminate the existing memory hierarchy. The practical goal is to place data according to its speed and capacity needs rather than require every reusable byte to remain in local accelerator memory.
- Local HBM: Memory attached to the accelerator remains the fastest tier for data the GPU needs immediately.
- Module HBM cache: The memory module’s HBM cache sits in front of its larger DDR5 capacity, helping bridge the performance gap between accelerator-local memory and the shared pool.
- Shared DDR5 capacity: The larger pool provides capacity for selected data, especially warm KV cache, that may be reused by AI workloads.
- Optical fabric: Photonic Fabric NICs and chiplets connect hosts and modules so memory transactions can travel over optical links, including between racks.
Marvell’s rationale is that optical links can avoid some reach and power penalties associated with long electrical paths. That is an architectural claim; the available figures do not provide a directly comparable, independently measured power-per-byte result against other pooling designs.
Why is KV cache the target?
A large language model’s KV cache stores key and value state built as the model processes tokens. That state is needed to continue generating from an existing conversation or context. As contexts become longer, and as agentic sessions retain more prior interaction, KV cache can become a substantial memory demand.
If useful cache state cannot remain in the memory available to a workload, a system may need to recompute state or retrieve it from another storage tier. A warm shared tier is intended to keep reusable state accessible without dedicating all of the capacity to one GPU server. The potential benefit is most relevant when many workloads need more memory capacity than their accelerators can provide locally.
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This does not mean every context can be served from the pool at the same speed as local HBM. The stated near-NUMA latency is a vendor description of access across multiple racks, not a claim that remote memory matches local accelerator memory. Workload performance will depend on whether the data is in local HBM, the module cache or the larger DDR5 tier, as well as on access patterns and contention.
How might pooled memory change long-context inference?
The intended benefit is to make more reusable context available without scaling accelerator memory at the same rate as GPU compute. Marvell says its architecture can support up to 2–3x higher token throughput within the same data-center footprint and power envelope. That is a vendor target or claim, not an independent benchmark result established by the public materials.
For an inference operator, the question is not simply whether a pool is large. It is whether the system can keep the right KV-cache data warm, retrieve it with acceptable latency, and serve enough concurrent requests to offset the cost and complexity of the additional fabric. A larger pool may help avoid recomputation or trips to slower storage, but it does not automatically make a single request faster. Throughput and latency are different outcomes: a system may handle more tokens across concurrent requests without reducing the time for each individual token.
What the throughput claim does—and does not—tell you
- It is stated for the same data-center footprint and power envelope, according to Marvell’s 2026 announcement.
- It is an “up to” figure, not a guaranteed gain for every model, context length, batch size or serving stack.
- The public claim does not establish independently measured results, test conditions, or a production customer deployment.
- It should not be compared directly with a research simulation unless workload, system configuration and measurement method match.
How does photonic pooling compare with CXL and Ethernet/RDMA?
These approaches all aim to extend memory capacity beyond an accelerator’s local memory, but the available figures do not support a complete apples-to-apples ranking. Photonic Fabric is positioned around optical memory access across hosts and racks; CXL expands memory over a memory interconnect; Ethernet/RDMA can connect systems over a network. The exact latency, bandwidth, cost and compatibility depend on implementation.
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| Approach | Capacity figure established here | Latency and reach established here | Bandwidth established here | What is not established in the cited materials |
|---|---|---|---|---|
| Marvell Photonic Fabric | Up to 32 TB of warm KV-cache offload at appliance level; module has up to eight DDR5 DIMMs and 72 GB HBM cache. | Marvell describes approximately less than 350 ns near-NUMA access across multiple racks and reach up to 50 m. | Up to 7.2 Tbps optical-fabric bandwidth per module, per Marvell. | Public price, independently measured appliance throughput, final shipping configuration, production-customer deployments, cost per GB and measured power per transferred byte. |
| Enfabrica EMFASYS, a CXL/RDMA contrast | Enfabrica advertises up to 18 TB of CXL DDR5 per system, expandable to 28 TB. | Not stated in the cited Enfabrica material summarized here. | Advertised over 400G/800G RDMA Ethernet; the source does not provide a directly comparable pooled-memory bandwidth figure. | Comparable memory-access latency, rack-to-rack reach, cost per GB, power per byte and independently measured performance. |
| Photonic-CXL research architecture | A related paper describes 32 TB across 16 hosts. | Not stated here as a directly comparable appliance result. | Not stated here as a directly comparable appliance result. | Equivalence to Marvell’s appliance, commercial availability, cost and production deployment. |
| Ethernet/RDMA pooling generally | Not stated as a general capacity figure. | Not stated as a comparable general latency or reach figure. | Varies by system; the Enfabrica example advertises 400G/800G RDMA Ethernet. | One universal performance, compatibility or cost profile; these depend on the system and workload. |
The table’s missing comparisons are meaningful: the public figures cited here do not establish a universal winner on cost, latency, software compatibility or deployment maturity. Enfabrica’s advertised 18 TB per system and expansion to 28 TB provide a concrete capacity comparison, but do not show that its system and Marvell’s appliance serve the same memory semantics or workload in the same way.
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What do the research results say about photonic pooling?
Columbia University researchers reported simulated improvements of 5.4x–7.5x in deep-learning training and inference time for a photonic pooling architecture in 2025. Because the result is from a simulation, it should not be presented as a measured improvement from a deployed Marvell appliance or as a prediction for every real-world AI server.
That result and Marvell’s 2–3x token-throughput claim describe different evidence and outcomes. The Columbia result concerns simulated training and inference time; Marvell’s figure is a vendor claim about token throughput within a stated footprint and power envelope. Neither number alone tells an operator what gain a specific production workload will see.
What should an AI infrastructure team verify before deployment?
Capacity figures and architectural goals are not enough to decide whether a shared memory tier fits a serving stack. Teams should validate the behavior of their own models, cache policies and accelerator systems against the specific appliance configuration offered.
- Capacity accounting: Confirm what the quoted pool includes, how much is usable for KV cache, how it is divided among tenants and whether the 32 TB figure applies to the offered configuration.
- Access behavior: Ask for measured latency distributions under the intended concurrency and rack topology, rather than relying only on an approximate near-NUMA figure.
- Workload results: Measure throughput and request latency separately using representative context lengths, batch sizes and concurrent sessions.
- Failure and recovery: Establish what happens to cached state when a module, link or host becomes unavailable, and whether workloads fall back to recomputation or another tier.
- Software integration: Confirm required drivers, host interfaces, cache-management software and supported accelerator configurations. The public descriptions cited here do not specify a complete software compatibility matrix.
- Operating economics: Compare total system and operating costs with the alternatives available to the organization. Public pricing and cost-per-GB figures are not established in the cited materials.
What is established, and what remains uncertain?
Marvell’s public materials describe the module composition, optical-fabric role, 50-meter reach claim, approximate near-NUMA latency, warm KV-cache workload and vendor throughput target. They also state maximum module figures of eight DDR5 DIMMs, 72 GB of HBM cache and 7.2 Tbps of optical-fabric bandwidth, alongside an appliance-level target of up to 32 TB.
Those facts establish the intended architecture and advertised scale, not a generally available product’s final bill of materials or measured performance. The cited materials do not establish public pricing, named production customers, independently measured appliance throughput, final shipping configuration or verified reseller terms. Treat the figures as vendor specifications and claims unless a deployment-specific test supplies the missing evidence.
Frequently Asked Questions
Is 32 TB enough for every model’s KV cache?
There is no single answer: cache consumption depends on the model and how much context and session state a workload retains. The 32 TB figure is an aggregate appliance target, so operators need to size capacity against their own request mix and allocation policy rather than assume it represents a fixed number of conversations.
Can a server use pooled memory if its GPU has no free HBM?
The architecture is intended to provide a tier beyond local accelerator memory, but that does not make remote DDR5 interchangeable with HBM or guarantee that every application can use it transparently. Compatibility depends on the particular host, accelerator and software integration offered.
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Does a larger KV-cache pool reduce the time for each token?
Not necessarily. The stated throughput improvement concerns tokens served within a fixed footprint and power envelope; higher aggregate throughput does not by itself prove lower per-request token latency.
Are the 5.4x–7.5x photonic pooling gains a real-world benchmark?
No: the cited Columbia University result is from a simulated architecture, not a published production-appliance test. Its figures should not be treated as an expected gain for a particular server deployment.
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