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AI data centers connect GPUs through several coordinated networks rather than one giant switch. Inside a server or rack, NVLink and NVSwitch-style systems provide the scale-up path between accelerators. Between servers, an RDMA-capable leaf-spine or fat-tree fabric carries the east-west traffic generated by training collectives. Separate north-south and management networks handle storage, provisioning, user access, and device administration.
This arrangement matters because distributed GPUs constantly exchange gradients, activations, parameters, and collective-operation results. If the fabric drops packets, builds queues, or lacks enough parallel paths, accelerators wait instead of computing. The most effective design therefore treats networking as part of the distributed computer: it must be fast, predictable, fault-tolerant, observable, and matched to the workload.
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What is a GPU network fabric?
A network fabric is the complete set of links, network adapters, switches, routing rules, congestion controls, and management systems that move data through an AI cluster. It is more than a collection of cables. The fabric determines how quickly GPUs can exchange data with one another, how traffic is balanced across paths, and whether a failure in one component stalls an entire job.
AI training is especially demanding because many GPUs perform the same phase of a computation at nearly the same time. They then exchange intermediate data in collective operations such as all-reduce, all-gather, and broadcast. A network that works well for ordinary web traffic can still perform poorly when thousands of endpoints generate synchronized bursts.
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Most modern designs divide communication into three domains:
- Scale-up: accelerator-to-accelerator communication inside a server or rack.
- GPU compute east-west: node-to-node and rack-to-rack traffic for distributed training and high-performance inference.
- North-south and management: storage, provisioning, user access, telemetry, and device administration.
Keeping these domains distinct lets architects optimize each one instead of forcing latency-sensitive GPU traffic to compete with storage or administrative transfers.
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How are GPU communications divided between scale-up, scale-out, and management networks?
Scale-up inside a server or rack
NVLink and NVSwitch-style domains connect accelerators over a tightly controlled topology. This is the scale-up layer: GPUs can exchange data without sending every transfer through the routed data-center network. The design question is how large this local domain should be before traffic crosses into the scale-out fabric.
A larger scale-up domain can reduce the number of routed hops for frequent accelerator exchanges, but it also increases the complexity of backplanes, switches, power, cooling, and failure handling. The boundary should be chosen from the workload’s communication pattern, not simply from the maximum number of GPUs that can fit in a chassis or rack.
GPU compute east-west fabric
Traffic between nodes uses an RDMA-capable fabric, commonly arranged as a leaf-spine or fat-tree network. In NVIDIA’s NVL72 design, each GPU position is connected through a corresponding SuperNIC in a rail-optimized pattern. Matching GPU positions across trays map to corresponding leaves, creating balanced paths through the network.
The compute fabric is engineered for collective traffic rather than occasional bursts. Nonblocking capacity, predictable hop counts, and multiple independent planes reduce the chance that one oversubscribed link becomes a cluster-wide bottleneck.
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North-south and management fabrics
A separate converged network carries storage, provisioning, user access, and in-band management. An out-of-band network isolates baseboard-management controllers and device-management traffic from user workloads. This separation limits interference and gives operators a way to reach equipment even when the production fabric is congested or misconfigured.
How does a collective operation move between GPUs?
Distributed frameworks divide a model or data set across many GPUs. At synchronization points, the GPUs execute collectives such as all-reduce, which combines values from every participant, or all-gather, which distributes each participant’s data to the others. Broadcast sends one source’s data to many receivers.
In a RoCE v2 implementation, a collective can be represented as RDMA_SEND and RDMA_WRITE actions. The resulting packets travel through Ethernet and IP, use UDP transport, carry InfiniBand-derived RDMA semantics, and include payload integrity checks. The exact packet path depends on the routing and collective software, but the data movement is designed to avoid unnecessary CPU copies.
What RDMA changes
Remote direct memory access allows a network adapter to place data directly into registered application memory. The CPU does not have to copy every message between kernel buffers and the application, reducing host overhead and memory traffic. That matters when a training job generates many simultaneous transfers while the CPUs are also feeding and coordinating the GPUs.
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1Scan for outdated or missing drivers - takes under a minute2Repair Windows errors before they cause bigger problems3Fix the driver behind crashes, sound loss and screen glitchesRDMA is not an automatic performance guarantee. It still requires suitable queueing, congestion control, routing, priorities, telemetry, and failure handling. InfiniBand provides a purpose-built RDMA fabric. RoCE carries RDMA semantics over Ethernet, so operators must engineer the Ethernet network to behave predictably under synchronized load.
Why synchronized bursts are difficult
Collectives can cause many senders to transmit at once toward the same set of receivers. If the fabric is oversubscribed, queues grow and packets may be delayed or dropped. Because the GPUs wait for collective phases to complete, a small network bottleneck can reduce utilization across an entire job rather than just slowing one transfer.
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How do leaf-spine and fat-tree fabrics keep thousands of GPUs connected?
Leaf-spine and fat-tree topologies provide a repeatable number of hops between endpoints and scale by adding leaves and spines. A well-sized design gives each leaf enough uplink capacity to reach the spines without creating an avoidable choke point.
Rail-optimized wiring
Rail optimization maps the same GPU position across trays or servers to corresponding network paths. Instead of wiring GPUs arbitrarily, the design preserves parallelism across leaves, SuperNICs, and spines. This helps collective libraries distribute traffic evenly and avoids making one NIC-to-switch connection a single point of failure.
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Multiple compute planes
NVL72 uses two compute planes. NCCL and the ConnectX-8 SuperNIC balance traffic across active planes. If one plane fails, communication continues on the other, but available bandwidth falls in proportion to the capacity that was lost. The failure is therefore contained to a defined domain instead of taking the whole cluster offline.
Nonblocking versus oversubscribed designs
A nonblocking fabric provides enough aggregate path capacity for all attached endpoints to transmit simultaneously at their designed rates. That is valuable for all-reduce and similar operations that create synchronized bursts. Oversubscription can lower cost or port count, but it must be deliberate: the ratio, affected traffic classes, and expected collective pattern should be measured and documented.
What is the difference between NVLink, InfiniBand, Ethernet with RoCE, UALink, and Ultra Ethernet?
| Technology | Primary role | Strengths | Main design question |
|---|---|---|---|
| NVLink/NVSwitch | Scale-up inside a node or rack | Very high-bandwidth accelerator communication with a tightly controlled topology | How large should the scale-up domain be before traffic crosses the routed fabric? |
| InfiniBand | Scale-out GPU compute | Purpose-built low-latency RDMA fabric with mature collective-communication tooling | Can the organization operate the specialized fabric and its telemetry stack? |
| Ethernet with RoCE/Spectrum-X | Scale-out and converged services | Ethernet ecosystem, routability, and the ability to combine compute, storage, and tenant services with isolation | Are losslessness, congestion control, and performance isolation engineered well enough for the workload? |
| UALink | Emerging open scale-up interconnect | Accelerator-to-switch load, store, and atomic semantics with multi-vendor standardization goals | Which products and software ecosystems will reach production maturity? |
| Ultra Ethernet | Open Ethernet evolution for AI and HPC | Full-stack work across NICs, switches, optics, cables, congestion signaling, and in-network collectives | Which specification revision and interoperable implementations are available at deployment time? |
NVIDIA positions Spectrum-X for accelerated RoCE and deterministic latency, while its Quantum InfiniBand products target low-latency AI training and high-performance computing. These are architectural choices, not universal rankings: the right option depends on the organization’s operating skills, software stack, isolation requirements, and workload communication pattern.
What do the published NVL72 bandwidth figures mean?
The following figures come from NVIDIA’s documented NVL72 logical architecture. They describe that configuration, not a guaranteed requirement for every AI cluster.
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| Metric | Documented value | How to interpret it |
|---|---|---|
| GPU compute uplinks per service unit | 144 × 400G | Aggregate uplink count and speed allocated to GPU compute traffic in the documented service unit |
| CPU traffic uplinks per service unit | 36 × 400G | Separate uplink capacity for CPU-related traffic |
| Customer-network bandwidth per GPU | Minimum 25 Gb/s | Minimum shown for the documented customer-network configuration |
| Storage bandwidth per GPU | 12.5 Gb/s | Storage bandwidth shown for that configuration |
These numbers illustrate why network planning must include more than switch port speed. Designers also need to account for the number of GPUs per service unit, rail mapping, breakout arrangements, cable reach, optics, and whether storage or customer traffic shares any physical or logical paths.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How should you design a GPU network fabric?
- Classify the workload. Decide whether the cluster will run large-scale training, fine-tuning, inference, or a mixed schedule. Training with frequent all-reduce operations places different demands on the fabric than inference serving with request-level communication.
- Set the scale-up boundary. Determine which GPU exchanges stay inside a server or rack over NVLink-class links and which must traverse the routed fabric.
- Choose the scale-out technology. Compare InfiniBand with RoCE Ethernet using operational capability, collective-library support, congestion behavior, tenant isolation, and required telemetry—not only headline link rates.
- Build the topology. Map GPUs, SuperNICs, leaves, and spines so each GPU has balanced paths. Use a nonblocking design where synchronized collectives require it, or document the intended oversubscription ratio and its consequences.
- Provide independent paths. Use multiple compute planes or equivalent redundancy so one cable, NIC, leaf, or plane failure does not isolate a whole job.
- Engineer RDMA controls. Configure queueing, priorities, congestion signaling, and failure handling as one system. RDMA without congestion management can simply move the bottleneck into switch buffers.
- Separate service traffic. Keep storage, provisioning, user access, and management traffic isolated from GPU east-west traffic. Maintain an out-of-band path for BMC and device administration.
- Validate the physical layer. Check optics, cable reach, breakout compatibility, port speeds, power delivery, and cooling at the target configuration. A topology that works on a diagram can fail if the selected transceivers or cable assemblies cannot meet the reach or thermal limits.
- Test failure behavior. Verify that traffic rebalances when a plane or link is removed, and measure the resulting bandwidth reduction. Confirm that management access remains available during a production-fabric incident.
- Instrument the fabric. Collect link counters, queue and congestion indicators, error rates, and collective-level timing. Correlate network events with GPU utilization so operators can distinguish a network bottleneck from a compute or storage problem.
What are the most common design and operations mistakes?
Treating every network as interchangeable
Using the same design for scale-up, GPU east-west, storage, and management can create contention and obscure failures. Give each traffic domain an explicit role and failure boundary.
Buying bandwidth without checking topology
High-speed ports do not eliminate a bottleneck if too many of them converge on an undersized uplink or an oversubscribed spine. Review aggregate capacity at every layer, including breakout links and service-unit boundaries.
Assuming RDMA removes congestion
RDMA reduces host-copy overhead, but it does not repeal queueing theory. Synchronized collectives still require careful congestion signaling, priorities, and telemetry.
Ignoring software and operations
InfiniBand, RoCE, and emerging standards differ in tooling, firmware, diagnostics, and staff skills. A fabric that is theoretically fast but difficult to monitor or repair can produce lower effective throughput than a simpler design.
Failing to test degraded operation
Redundancy is meaningful only if routing and collective software actually use the surviving paths. Test single-link, NIC, leaf, and plane failures before relying on the design for long training runs.
What is changing in open network standards?
The Ultra Ethernet Consortium released Specification 1.0 on June 11, 2025. It defines an Ethernet-based, interoperable stack spanning NICs, switches, optics, and cables. The consortium’s specification history lists Specification 1.1, released October 12, 2026, as the current published revision; it adds scale-up optimizations, in-network collectives, congestion signaling, and programmable congestion management.
UALink addresses the scale-up boundary. Its 200G 1.0 specification defines low-latency accelerator-to-switch communication for up to 1,024 accelerators in an AI pod. The consortium incorporated in 2024 and published its first specification in April 2025.
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Scan for outdated or missing drivers - takes under a minuteDriver Scan →Clear out junk files and repair common Windows errorsFree Scan →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Those milestones show where the standards are heading, but a specification is not the same as broad production deployment. Buyers should verify compatible silicon, switches, cables, firmware, collective libraries, and management tools for the exact products they plan to operate.
How can you tell whether a fabric is limiting GPU performance?
Start with collective timing and GPU utilization rather than looking only at average link throughput. If GPUs repeatedly become idle at synchronization points, compare the timing of those stalls with switch queue growth, retransmissions or errors, path changes, and per-rail imbalance.
- Check whether one leaf, spine, rail, or NIC carries materially more traffic than its peers.
- Inspect congestion and priority counters during the exact training phase that shows stalls.
- Run the same workload with a reduced GPU count to see whether the problem appears only after a topology boundary is crossed.
- Remove one redundant path under controlled conditions and verify that traffic continues with the expected proportional bandwidth loss.
- Confirm that storage and provisioning transfers are not sharing queues or links with collective traffic.
This approach distinguishes a fabric-capacity problem from an application imbalance, slow storage, CPU starvation, or a faulty accelerator.
Frequently Asked Questions
Do all GPUs in an AI cluster need a direct connection to every other GPU?
No. Scale-up links may provide dense local connectivity, while scale-out traffic is routed through leaves and spines. What matters is that the topology offers enough balanced paths and collective bandwidth for the workload; a full mesh between every GPU would be impractical at large scale.
Can a RoCE Ethernet fabric carry storage and GPU traffic at the same time?
Yes, but only with explicit traffic classes, isolation, and congestion controls. The design should reserve predictable treatment for GPU collectives and verify that storage bursts cannot fill the queues needed by east-west compute traffic.
What bandwidth should I plan for each GPU?
There is no universal number because the requirement depends on model size, collective frequency, scale-up links, and the chosen cluster architecture. NVIDIA’s documented NVL72 configuration lists a minimum 25 Gb/s customer-network bandwidth and 12.5 Gb/s storage bandwidth per GPU, figures that apply to that configuration rather than every deployment.
Is UALink already a replacement for NVLink?
The available information establishes UALink as an open scale-up standard with a 200G specification supporting up to 1,024 accelerators in an AI pod. It does not establish that UALink has displaced NVLink in deployed clusters, so production decisions should be based on available hardware and software ecosystems at deployment time.
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