HBM4E is the extended high-bandwidth memory generation after HBM4, designed for AI accelerators and other high-performance computing systems. Samsung and SK hynix have announced customer samples with higher reported data rates and bandwidth than their HBM4 products, as well as larger stack options. The numbers are vendor- and configuration-specific, however: they are not a single universal HBM4E rating, and sample shipments do not mean the memory is available as a consumer upgrade.
What is HBM4E?
HBM4E is an extended product generation following HBM4. SK hynix describes it as a response to the bandwidth, capacity and power-efficiency needs of next-generation AI systems. Like other HBM generations, it is intended to be integrated into computing systems rather than sold as a regular desktop memory module.
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High-bandwidth memory (HBM) is DRAM whose memory dies are stacked vertically and connected using through-silicon vias (TSVs). The stack is designed to move data at high throughput for processors used in AI and high-performance computing, unlike conventional DDR memory, which serves general-purpose computing. Samsung explains the stacked-die and TSV design in its HBM overview; Micron discusses HBM’s role in AI and HPC in its HBM4 explainer.
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Two measurements matter when comparing HBM: capacity, or how much data a stack can hold, and bandwidth, or how quickly it can transfer data to and from the processor. A larger capacity does not by itself mean higher bandwidth, and a bandwidth figure does not tell you how much memory the stack contains.
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How is HBM4E different from HBM4?
Manufacturers report higher per-pin data rates and greater bandwidth for HBM4E than for their HBM4 products, along with 48 GB 12-layer configurations and a Samsung-stated 64 GB 16-layer option. These figures describe different vendors and configurations, not a controlled, like-for-like comparison. The table summarizes the published claims and their context.
| Measure | HBM4E claims | HBM4 comparison | How to interpret it |
|---|---|---|---|
| Per-pin data rate | SK hynix reports a maximum of 16 Gbps per pin. Samsung reports 14 Gbps stable operation, scalable up to 16 Gbps. | Samsung reports 11.7 Gbps in system-in-package tests and lists speeds up to 13 Gbps on its HBM product page. SK hynix says its HBM4 implementation exceeded 10 Gbps, compared with the 8 Gbps JEDEC speed cited in its announcement. | Operating points and test contexts differ; these are company-reported figures, not one guaranteed rate for every product. |
| Bandwidth per stack | Samsung announced up to 3.6 TB/s for a 12-layer HBM4E sample and later described a 4.0 TB/s HBM4E demonstration at GTC 2026. | Samsung lists up to 3,300 GB/s for HBM4. Micron describes more than 2.8 TB/s for a 12-high HBM4 stack. | The 4.0 TB/s figure is a Samsung demonstration claim; it should not be combined with the separate 3.6 TB/s sample claim as though both describe the same configuration or test. |
| Capacity and stack height | SK hynix announced a 48 GB, 12-layer stack. Samsung announced a 48 GB, 12-layer sample and says it plans 32 GB 8-layer and 64 GB 16-layer configurations to customer requirements. | Samsung lists a 36 GB, 12-high HBM4 product. Micron also describes a 36 GB, 12-high HBM4 stack. | The 64 GB figure is for a stated 16-layer option, not the same configuration as a 48 GB 12-layer sample. |
| Power and thermal claims | SK hynix reports over 20% higher power efficiency and 17% improved heat resistance versus its preceding HBM4. Samsung reports 16% improved energy efficiency and more than 14% improved thermal resistance versus its previous generation. | SK hynix reported a power-efficiency improvement above 40% for its HBM4 compared with its prior generation. | These are different vendors’ claims against different baselines and methods, not direct head-to-head results. |
| Implementation | SK hynix identifies Advanced MR-MUF for its 48 GB 12-layer product. Samsung cites 1c DRAM and a 4 nm logic base die. | Samsung also cites 1c DRAM and a 4 nm logic base die for its HBM4. | These are manufacturer-specific implementation details, not defining features of every HBM4E product. |
The figures in the table come from company materials: SK hynix’s HBM4E sample announcement, Samsung’s HBM4E sample announcement, Samsung’s HBM product page, Micron’s HBM4 explainer, and Samsung Semiconductor’s GTC 2026 announcement. They do not establish independent, apples-to-apples performance measurements or a finalized public HBM4E standard.
How much faster is HBM4E?
There is no single percentage that captures how much faster HBM4E is than HBM4. A per-pin data rate describes transfer speed at an individual connection; bandwidth per stack describes aggregate data transfer for a particular memory stack. Published HBM4E figures reach 16 Gbps per pin in vendor claims and, in Samsung’s separate demonstration, 4.0 TB/s per stack. Those values come from different contexts and should not be treated as one tested product specification.
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How much memory can an HBM4E stack hold?
The announced capacities depend on the number of layers and vendor. SK hynix and Samsung have each announced a 48 GB 12-layer HBM4E configuration. Samsung also says it plans customer-specific 32 GB 8-layer and 64 GB 16-layer configurations. Treat these as distinct stack options: the 64 GB option has more layers than the 48 GB sample, so it is not a like-for-like comparison.
Is HBM4E available yet?
As of October 7, 2026, Samsung and SK hynix have announced shipments of HBM4E samples to major customers. SK hynix’s announcement is dated June 18, 2026; Samsung says mass production will align with customer schedules after sample shipments and optimization. These announcements establish customer sampling, not general retail availability or one production start date shared by both companies.
HBM4E is a component intended for integration into accelerator and other high-performance computing systems. The announcements do not describe it as a standalone module that consumers can buy and install in a desktop PC.
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