Deep ultraviolet (DUV) lithography uses light to project a chip pattern from a mask onto a light-sensitive coating on a silicon wafer. The pattern is developed and transferred into the materials beneath it through later manufacturing steps. DUV is one part of chipmaking—not a process that creates a finished transistor by itself—and it remains widely used, including on chips that also use extreme ultraviolet (EUV) lithography.
What DUV lithography does
A useful way to picture lithography is as a blueprint projected onto a temporary recording layer. The blueprint is a patterned mask, also called a reticle. The recording layer is photoresist, a coating that changes chemically when exposed to light. Lenses in the scanner reduce and focus the reticle’s image onto the wafer. After exposure, baking and chemical development reveal a resist pattern that guides later steps such as etching or ion implantation.
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Lithography defines where subsequent manufacturing processes act. It does not, on its own, make a transistor or complete a chip. Chip structures are built through repeated cycles of depositing material, coating the wafer with resist, exposing and developing a pattern, etching or otherwise modifying the underlying layer, and removing resist. ASML says lithography may be repeated 100 times or more across a chip, depending on its design and process (ASML’s lithography overview; ASML 2024 Annual Report, published in 2025).
The Tool Desk
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- Prepare the wafer. A layer of photoresist is applied to the wafer, which already contains structures from earlier manufacturing steps.
- Illuminate the reticle. A DUV excimer laser sends light through or from a patterned reticle. ASML describes the reticle pattern as four times larger than the intended pattern on the chip.
- Project and scan. In a step-and-scan machine, a narrow strip of the reticle is illuminated as the reticle and wafer move in opposite directions. The optics project a 4:1 reduced image onto the wafer.
- Step to the next die position. After scanning one die’s pattern, the wafer moves to another position for the next exposure. The sequence repeats across the wafer.
- Develop and transfer the pattern. Baking and chemical development turn the exposed resist into a physical pattern. Etching, implantation, or another process uses that pattern to modify the layer below, after which the resist is removed.
The NIST-hosted handbook chapter on nanoelectronics lithography describes the step-and-scan method and the chemical processing used to turn the latent resist image into a patterned structure (NIST-hosted handbook chapter). The exact sequence and number of exposures vary by chip design and manufacturing process.
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- The pattern is produced by light diffraction, and its reflective appearance changes with the viewing angle.
- Silicon wafers are fragile—please handle with care.
- Circuit details can be examined under a microscope.
DUV wavelengths and what determines feature size
DUV scanners use excimer lasers. Two important sources are krypton-fluoride (KrF), which emits at 248 nanometers, and argon-fluoride (ArF), at 193 nanometers. Shorter wavelengths can help print smaller features, but wavelength is only one factor. Resolution also depends on the optical system’s numerical aperture (NA), process conditions, and photoresist behavior.
ASML gives illustrative examples in its technical explanation: modern KrF systems can produce features down to 80 nm, while 193 nm ArF enabled 38 nm feature sizes. These are vendor examples, not universal limits for every process or scanner. A chip’s process-node label should not be treated as a direct statement of the smallest feature a particular lithography tool can print.
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The Rayleigh criterion expresses the relationship among wavelength, NA, and process-dependent factors that affect printable feature size. NA describes how well an optical system collects and focuses light. Increasing NA can improve resolution without changing the light source’s wavelength (ASML on lithography optics).
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In immersion lithography, a thin layer of water sits between the scanner’s final lens and the wafer. Water’s refractive index allows the optical system to achieve an NA above 1, improving resolution at the same wavelength. The water does not change the wavelength of the DUV light.
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ASML reports an NA of 1.35 for its highest-resolution DUV machines. Its 2024 Annual Report, published in 2025, identifies the TWINSCAN NXT:2150i as a 193 nm ArF system with NA 1.35 and a throughput of up to 310 wafers per hour. Those are vendor-reported specifications for that particular tool, not a general DUV production rate (ASML 2024 Annual Report).
How DUV compares with EUV
EUV uses light at 13.5 nm—more than 14 times shorter in wavelength than DUV, according to ASML. That shorter wavelength can support finer patterning. EUV scanners use mirrors and operate in a vacuum; DUV systems use refractive optics and either a dry optical path or water immersion, depending on the system. The difference is not simply “old” versus “new”: chipmakers choose lithography methods layer by layer according to the pattern and process.
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| Approach | Light source | Optical path | Patterning role and tradeoffs |
|---|---|---|---|
| KrF DUV | 248 nm excimer laser | DUV projection optics | ASML says modern KrF systems can produce features down to 80 nm; actual results depend on the system and process. |
| ArF DUV | 193 nm excimer laser | Dry or water immersion, depending on the system | Immersion raises NA and can improve resolution. Multi-patterning can extend DUV to dense layouts but adds exposures and alignment demands. |
| EUV | 13.5 nm light | Mirrors in a vacuum | Its shorter wavelength can simplify some intricate patterns that would otherwise require complex DUV multi-patterning; it does not replace DUV across every chip layer. |
ASML says DUV systems remain industry workhorses and produce the majority of microchip layers. EUV and DUV can both be used on the same chip: EUV may pattern especially intricate layers while DUV handles many others. The sources do not establish a single process flow or a universal DUV resolution limit for all manufacturers (ASML 2024 Annual Report; ASML’s lithography principles).
How multi-patterning extends DUV
When one exposure cannot print a desired dense layout, multi-patterning divides it into simpler interlaced patterns and exposes them separately. Combining those patterns requires precise alignment, known as overlay. More patterning steps bring additional process complexity and cost. ASML says EUV can simplify manufacturing compared with complex multi-patterning strategies using DUV immersion (ASML 2024 Annual Report).
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- Why use it: Separate exposures can create a denser pattern than a single exposure could reliably produce.
- What it demands: The separately printed patterns must align accurately on the wafer.
- The tradeoff: Additional exposures and processing make the manufacturing flow more complex.
What throughput figures do—and do not—mean
Scanner throughput is the number of wafers a machine can expose in a given time under stated conditions; it is not the number of finished chips a fab produces per hour. The NXT:2150i figure of up to 310 wafers per hour is ASML’s specification for that 193 nm ArF, NA 1.35 machine. Separately, the NIST-hosted handbook chapter describes a typical leading-edge scanner example as more than 50 full-chip exposures on a 300 mm wafer and about 100 wafers per hour. The chapter’s publication year is not established on the cited page, so that figure is historical context, not a current tool benchmark (NIST-hosted handbook chapter).
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