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Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstallASML makes the highly specialized equipment, software and services that semiconductor manufacturers use to print and control circuit patterns on silicon wafers. It does not manufacture finished CPUs, GPUs or memory chips. Its systems are part of the fab’s production line: lithography exposes patterns, metrology measures what was printed, inspection finds defects, and software feeds those measurements back into the next exposure.
The company is strategically essential because its extreme ultraviolet (EUV) systems use 13.5-nanometer light to print the most intricate layers in leading-edge chips. Deep-ultraviolet (DUV) tools, inspection, metrology and process-control software remain necessary around those EUV steps, so modern chipmaking depends on an integrated equipment-and-software workflow rather than on one machine alone.
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What ASML actually makes
ASML is an equipment and technology supplier to chip fabs. Its portfolio spans pattern-printing machines, measurement and inspection systems, computational-lithography software, process-control tools and long-term service. ASML describes its machines as an essential part of chip manufacturing because they transfer the chip designer’s patterns onto wafers with nanometer-scale precision.
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EUV lithography systems
Extreme ultraviolet lithography systems print the smallest features at the highest pattern density. ASML’s 2025 strategic material says EUV uses 13.5-nanometer light and is used for the most intricate, critical layers of advanced logic and memory devices. The company’s 2025 annual-report material states that ASML was then the world’s only manufacturer of EUV lithography systems; that is a time-sensitive company statement, not a permanent guarantee about the industry.
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EUV tools are not used for every layer. A fab selects the exposure technology that fits each layer’s dimensions, alignment requirements and production economics. EUV is reserved for layers where its resolution and patterning advantages justify the complexity.
DUV lithography systems
Deep-ultraviolet systems cover a broad range of chip layers and remain essential in mainstream production, including advanced chips. When a feature cannot be printed in one DUV exposure, the fab can use multi-patterning: several masks and process steps divide one difficult pattern into exposures that the DUV tool can resolve.
ASML reported 279 DUV system sales in calendar year 2025. That figure illustrates why EUV has not replaced DUV. A chip requires many layers, and most of those layers still use DUV or other process steps selected for their required resolution and cost.
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Printing a pattern is only half the manufacturing problem. The fab must verify that lines, spaces and layer-to-layer alignment match the design, then identify defects before they reduce yield. ASML’s YieldStar optical-metrology family measures overlay and other printed dimensions, including post-etch process control. Its HMI electron-beam systems inspect wafers and support defect detection and metrology; machine-learning methods can improve detection and help determine where inspection samples should be taken.
Computational lithography and process control
Chip patterns distort as light passes through optics, masks and photoresist and as wafers move through multiple process steps. Computational-lithography software models those effects and modifies the mask pattern or exposure settings so the wafer result is closer to the intended design. Process-control software then uses measurements from the line to optimize each exposure and make chip-by-chip in-line adjustments.
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ASML’s 2025 filing says the hardware alone could not manufacture ever-smaller features without this process-control software. In practical terms, the software closes the loop between what the design requests, what the scanner exposes and what metrology and inspection observe on the wafer.
Installation, upgrades and lifecycle support
ASML supplies more than a scanner delivered to a cleanroom. Its mass-production offering includes installation, software, upgrades, field support and lifecycle assistance. These services keep a tool calibrated, productive and compatible with changing process recipes over years of operation.
How a lithography system turns a design into a wafer pattern
A lithography step transfers one layer of a chip design to a wafer coated with light-sensitive photoresist. The exact chemistry and sequence vary by process, but the equipment workflow can be understood in five stages.
- Prepare the wafer. The fab deposits or grows the layer to be patterned, cleans the wafer and applies photoresist.
- Align the wafer. The scanner measures existing alignment marks and positions the wafer so the new pattern lines up with previously printed layers.
- Expose the pattern. Light passes through or reflects from a mask and is projected onto the wafer. The scanner steps or scans across the wafer field, repeating the pattern with controlled dose and focus.
- Develop and etch. Developing removes selected portions of photoresist. Subsequent deposition or etch steps transfer the resist image into the underlying material.
- Measure and correct. Metrology checks overlay and dimensions, while inspection looks for defects. Process-control software uses those results to adjust later exposures and process settings.
This loop repeats for many layers. A small overlay error on one layer can compound with errors on others, which is why exposure, measurement, inspection and software are treated as one manufacturing system.
Why EUV is so important to leading-edge chips
It prints critical features with fewer patterning steps
As transistor and memory structures shrink, some critical patterns become too difficult to print directly with DUV alone. EUV’s 13.5-nanometer wavelength lets a fab print those layers with a simpler single-pattern exposure in cases where DUV would require complex multi-patterning.
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Replacing several patterning passes with one can reduce the number of masks and process steps. The potential benefits are better scalability, fewer opportunities for alignment error, improved yield and lower manufacturing cost for that layer. The result depends on the specific process, so EUV is an enabler rather than an automatic cost reduction for every chip.
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ASML describes an EUV source that fires laser pulses at tin droplets in near vacuum. The impact creates a plasma that emits EUV light. Because most materials absorb this wavelength, the light travels through vacuum and is reflected by multilayer mirrors rather than sent through ordinary transparent lenses.
Productivity depends heavily on how much usable EUV light reaches the wafer. ASML reported demonstrating its first 1,000-watt EUV light source in April 2025, a milestone aimed at higher throughput. A source-power demonstration is not the same as a guarantee that every installed scanner runs at that power or achieves a particular wafer output.
EUV works only as part of a larger control system
Exposure accuracy is affected by focus, dose, wafer position, mask behavior and changes in the process. ASML’s “holistic lithography” approach links EUV and DUV scanners with YieldStar metrology, HMI e-beam inspection, computational lithography and process-control software. Measurements from one tool can guide corrections in another, allowing the fab to manage variation across wafers and across individual chips.
EUV and DUV compared
The two families are complementary, not mutually exclusive. The following comparison uses the capabilities and figures ASML reported for 2025; where a specific value was not established, it is identified as not stated.
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| Characteristic | EUV systems | DUV systems |
|---|---|---|
| Light source | 13.5-nanometer extreme-ultraviolet light | Deep-ultraviolet light; the specific wavelength is not stated in the cited ASML material |
| Typical role | Smallest, highest-density and most critical layers in advanced logic and memory | Broad range of layers, including mainstream production and layers in advanced chips |
| Patterning approach | Can replace multi-patterning with a single exposure for some critical layers | May require multi-patterning when one exposure cannot resolve a feature |
| Manufacturing-control needs | Used with overlay metrology, inspection and computational process control | Uses the same measurement and control loop to manage alignment, dimensions and defects |
| 2025 ASML system sales | 48 EUV lithography systems | 279 DUV lithography systems |
“Single exposure” does not mean a chip is made in one pass. It describes the way a particular layer is patterned. A complete device still requires many exposures and additional deposition, etch, clean and inspection operations.
Examples of ASML systems and their jobs
| System or family | What it does | Reported detail |
|---|---|---|
| TWINSCAN NXE:3800E | 0.33 numerical-aperture EUV lithography for high-volume production | ASML’s 2025 strategic report gives 220 wafers per hour for the full-specification version, a 37% improvement over NXE:3600D |
| TWINSCAN EXE:5200B | High-NA EUV lithography for more demanding patterning | ASML highlighted delivery of its first full-specification system to a customer in 2025 |
| TWINSCAN XT:260 | Lithography for advanced packaging and three-dimensional integration | Applications include image sensors, displays and photonics |
| YieldStar | Optical metrology for overlay and process measurements | Includes post-etch control applications |
| HMI e-beam systems | Electron-beam inspection and metrology | Machine learning is used to improve defect detection and inspection sampling |
The 220-wafer-per-hour figure applies to the full-specification NXE:3800E configuration under the conditions defined by ASML. It should not be treated as the output of every NXE:3800E installation or as a direct prediction of finished-chip volume.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Does ASML make chips?
No. Chip manufacturers buy or lease lithography, metrology, inspection and software systems from equipment suppliers such as ASML, then use those systems in their own fabrication plants. The manufacturers create the wafer process, operate the cleanroom and perform the deposition, etch, implantation, cleaning, packaging and testing that turn silicon wafers into finished processors, memory and other devices.
That division explains why ASML can be essential without appearing on a chip’s retail label. Its machines shape the microscopic structures inside the device, but the branded product is made and sold by the semiconductor company that runs the fab.
Why other companies cannot simply copy an EUV machine
ASML’s 2025 annual-report material identifies it as the world’s only manufacturer of EUV lithography systems at that time. The reason is not one isolated component that can be duplicated; an operational scanner requires many tightly coordinated capabilities.
- A stable EUV source: laser pulses must strike tin droplets in vacuum and deliver enough usable light for production.
- Reflective optics: EUV must be guided by multilayer mirrors because ordinary optical materials absorb it.
- Nanometer-scale stage and alignment control: the wafer and mask must move and align accurately across repeated fields and layers.
- Pattern and process modeling: computational lithography must compensate for optical and process effects.
- Measurement and inspection: overlay, dimensions and defects must be measured quickly enough to correct production.
- Factory integration and service: software, upgrades, calibration and field support must keep the system productive in a customer’s fab.
The defensible conclusion is that EUV is a system-integration challenge spanning optics, plasma physics, precision motion, software and factory operations. Competitive positions can change, and ASML’s “only manufacturer” statement should therefore be read with its 2025 date and attribution.
How large is ASML’s role in 2025?
ASML reported the following calendar-year 2025 figures:
| Measure | 2025 figure | What it represents |
|---|---|---|
| EUV lithography systems sold | 48 | Systems reported by ASML for calendar year 2025 |
| DUV lithography systems sold | 279 | Systems reported by ASML for calendar year 2025 |
| Metrology and inspection systems sold | 208 | Systems reported by ASML for calendar year 2025 |
| Total net sales | €32.7 billion | ASML’s calendar-year 2025 total net sales |
| Research and development | €4.7 billion | ASML’s calendar-year 2025 R&D spending |
These are company-reported totals, not a count of all equipment installed in the world or a measure of how many finished chips were produced. Shipment totals, revenue, product specifications, customer deployments and export rules can change from year to year.
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A modern fab cannot optimize only for the sharpest possible exposure. It must balance resolution, overlay, defect rates, throughput, uptime and the number of patterning steps. EUV may simplify a critical layer, while DUV handles other layers more economically. Metrology and inspection determine whether either exposure method is actually producing acceptable wafers, and software turns those measurements into corrections.
That interdependence is why a delay or limitation in one part of the lithography workflow can affect chip production even when the fab has enough wafers, chemicals and assembly capacity. Conversely, improvements such as the NXE:3800E’s reported throughput or a higher-power EUV source matter only when the surrounding process-control loop can maintain yield at the faster operating point.
What to check when a claim about ASML changes
ASML’s product roadmap and the semiconductor industry move quickly. When evaluating a newer claim, check four qualifications:
- Date: distinguish calendar-year shipment figures from a current product announcement.
- System configuration: verify whether a throughput number applies to a full-specification tool, a particular process or a laboratory demonstration.
- Role in the chip: determine whether the tool addresses a critical layer, many less demanding layers or measurement rather than exposure.
- Geography and rules: customer deployments and export controls can differ by country and can change after the cited report.
Those checks prevent a common misunderstanding: treating one EUV milestone as if it describes every lithography step, every fab or every finished chip.
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