ASML makes the lithography systems, light sources, software, metrology and inspection tools that chipmakers use to print circuit patterns on silicon wafers. It does not design or manufacture finished processors or memory chips. Its equipment projects patterns into photoresist, controls their placement and focus, detects defects and helps a fab repeat those steps across many layers at high yield. Extreme ultraviolet (EUV) systems use 13.5-nanometer light for the most intricate layers, while deep ultraviolet (DUV) systems handle many other layers in both advanced and mature processes.
What ASML actually makes
ASML describes itself as a company that designs and manufactures lithography machines, an essential part of chip manufacturing. In practice, its portfolio is broader than a single scanner. The company combines exposure hardware with light sources, control software, computational lithography, optical metrology, electron-beam (e-beam) metrology and inspection, and service activities. Together, these products form a process-control system for a semiconductor fab.
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Lithography systems
A lithography system, often called a scanner, aligns a wafer beneath an optical projection system and exposes selected areas of photoresist to a circuit pattern. The wafer is coated with a light-sensitive material; after exposure and development, the remaining resist acts as a temporary mask for etching or implantation. A scanner must position and expose each field repeatedly, maintain focus and overlay, and do so at production speed.
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DUV and EUV light sources
ASML develops the ultraviolet light sources used by its DUV and EUV systems. EUV systems use light with a 13.5-nanometer wavelength. DUV systems use other ultraviolet wavelengths, with the exact wavelength depending on the system generation. The wavelength is one of the main factors that determines how finely a pattern can be projected, although optics, numerical aperture, resist behavior and process conditions also matter.
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Software, metrology and inspection
ASML’s 2025 annual-report materials describe computational lithography, system control, optical metrology and e-beam metrology and inspection as parts of its offering. Software coordinates the scanner’s hardware and helps control imaging and pattern placement. Computational lithography is used to account for the behavior of the imaging and process steps when preparing and controlling patterns. Metrology measures whether features were printed where they should be, while inspection looks for defects that could lower yield. These capabilities turn a scanner into a feedback-controlled manufacturing tool rather than an isolated projector.
Does ASML make chips?
No. Chipmakers purchase or lease lithography systems and integrate them with deposition, etch, implantation, cleaning, packaging and other equipment in their own fabs. ASML supplies the patterning and control technology; it does not sell finished CPUs, GPUs, memory dies or other consumer semiconductors.
Where lithography fits in wafer fabrication
A chip is built by repeating a sequence of processes for many material layers. A simplified cycle looks like this:
- Deposition: a film is added to the wafer.
- Photoresist coating: the wafer receives a uniform light-sensitive resist layer.
- Lithography exposure: the scanner projects the selected circuit pattern into the resist.
- Baking and developing: thermal treatment and developer reveal the exposed or unexposed pattern, depending on the resist chemistry.
- Etching or ion implantation: the revealed pattern guides removal of material or placement of dopants.
- Photoresist removal and cleaning: the temporary mask is stripped before the next layer.
Lithography is the pattern-transfer step in this loop. It does not create the transistor or interconnect by itself; it defines where later etching and implantation will create those structures. Because the cycle is repeated across many layers, a small error can be repeated thousands or millions of times on one wafer. Resolution, overlay, focus and defect control therefore affect both the electrical performance of individual devices and the number of working dies a wafer produces.
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Why lithography is essential to advanced chips
Resolution sets the scale of printed features
Advanced chips contain extremely dense transistor and wiring patterns. The imaging system must resolve narrow lines, spaces and contacts while maintaining the intended shape. Shorter-wavelength EUV light gives the industry a way to print the smallest, most intricate critical layers at useful density. DUV remains important because many layers do not require EUV and because different layers can have different patterning requirements.
Overlay keeps layers aligned
A chip is not one two-dimensional picture. It is a stack of patterned layers, and each new layer must line up with structures already formed below it. Overlay is the placement error between those layers. Excessive overlay error can change a transistor’s dimensions, break a connection or reduce the margin available to later process steps. Lithography systems, alignment sensors, control software and metrology work together to keep that error within the process window.
Focus and uniformity protect yield
Exposure must remain in focus across the wafer and across every field. Variations in wafer topography, resist thickness, temperature or tool behavior can alter the printed pattern. A production fab monitors those variations and adjusts recipes and tool settings. Better control means more dies meet specifications instead of being rejected after expensive downstream processing.
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A technically capable scanner is not useful for high-volume manufacturing if it exposes wafers too slowly or requires excessive rework. Fabs evaluate imaging quality together with wafer throughput, uptime, overlay performance, defect levels and the stability of the process over time. ASML’s systems are therefore designed as production platforms, with hardware, software, service and measurement functions working together.
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EUV versus DUV lithography
EUV and DUV are complementary technologies, not mutually exclusive alternatives. A single advanced chip can use EUV for its most critical layers and DUV, including immersion DUV, for other layers. Mature-node products may use DUV throughout.
| Comparison | EUV | DUV |
|---|---|---|
| Light wavelength | 13.5 nanometers, according to ASML | Other ultraviolet wavelengths; the exact value depends on the DUV system |
| Primary job | Prints the smallest and most intricate critical layers at leading-edge density | Prints many layers across advanced and mature nodes |
| Minimum printable feature size | Enables finer features than earlier ultraviolet approaches; a universal minimum is not stated because it depends on the complete process | Feature size depends on wavelength, numerical aperture, resist and patterning scheme; no single minimum applies to all DUV systems |
| Patterning strategy | Can reduce the number of patterning steps needed for selected critical layers | May use multiple patterning for features below the direct imaging capability of a given system |
| Immersion | Uses EUV-specific optical architecture rather than the water-immersion approach used by immersion DUV | Immersion DUV is used for demanding layers and can be combined with EUV on the same chip |
| Typical node role | Leading-edge, high-density logic and memory layers | Both advanced layers that do not need EUV and mature-node production |
The table describes roles rather than a strict division by product name. Process engineers choose a tool for each layer based on the required pitch, overlay budget, throughput, defect performance and cost. EUV does not replace every DUV exposure, and DUV is not limited to old chips.
How an EUV exposure enables finer patterns
EUV’s 13.5-nanometer wavelength is much shorter than the wavelengths used by conventional DUV systems. In combination with high-numerical-aperture optics and a suitable resist and process flow, that shorter wavelength supports finer imaging. The practical benefit is not merely a smaller line on a specification sheet: selected layers can be printed with fewer patterning operations than would otherwise be required.
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Multiple patterning divides a dense pattern into several exposures and process steps. It can extend a DUV-based process, but every extra operation adds alignment opportunities, cycle time, defect risk and cost. EUV can consolidate some of those operations for the most intricate layers. The exact number of steps saved depends on the chip design and process, so it cannot be stated as one universal figure.
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High-NA EUV
ASML’s strategy materials say its newest High-NA EUV systems are intended to provide finer resolution and help move some layers from multiple patterning toward single patterning. “High NA” refers to a higher numerical aperture in the projection optics, which increases resolving capability but also changes the imaging and process-control requirements. Whether a particular layer uses High-NA EUV depends on the chipmaker’s process integration and economics; the technology is a path for future generations, not a claim that every current chip uses it.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Why ASML is difficult to replace
The scanner is an integrated platform
Replacing a scanner would not mean substituting one box for another. The system combines precision stages, projection optics, a light source, wafer and reticle handling, alignment, focus control and real-time software. The components must work together with nanometer-scale placement accuracy at production throughput. A weakness in any one part can erase the benefit of the others.
Control software is part of the manufacturing capability
ASML’s annual-report materials characterize its lithography systems as a hybrid of high-tech hardware and advanced software and state that manufacturing ever-smaller features would be impossible without the control software. The software manages exposure conditions and system behavior, coordinates measurements and supports corrections needed to keep patterns within the process window. This is why the equipment’s value cannot be judged by its light source or optics alone.
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Metrology and inspection close the feedback loop
A modern fab treats exposure as part of an integrated process-control loop. The loop combines exposure, computation, metrology and inspection: the tool prints a pattern, measurements determine how closely it matches the target, inspection identifies defects, and process engineers use that information to optimize recipes and control settings. Fast feedback can prevent a drift from affecting an entire lot of wafers.
Manufacturing knowledge accumulates over generations
Each generation of lithography depends on years of optical, mechanical, materials, software and manufacturing development. The challenge includes producing a stable light source, maintaining clean and precise optical paths, moving wafers and masks accurately, and servicing the system so performance remains consistent in a fab. The result is a tightly integrated industrial technology stack, not a single easily copied component.
What the 2025 annual report figures mean
ASML’s 2025 annual report lists 48 EUV lithography systems and 279 DUV lithography systems. Those are figures reported for that annual-report period, not permanent limits or a current inventory guarantee. Product counts and technology generations change as systems are shipped, upgraded and replaced.
| Figure | What it represents | Qualification |
|---|---|---|
| 48 | EUV lithography systems | Count stated in ASML’s 2025 annual report |
| 279 | DUV lithography systems | Count stated in ASML’s 2025 annual report |
| 13.5 nm | EUV wavelength | Technology specification stated by ASML; not a claim about every DUV system |
How a fab decides between EUV and DUV
Engineers assign a lithography technology layer by layer rather than labeling an entire chip “EUV” or “DUV.” They consider:
- Pattern density and pitch: the most crowded layers may require EUV or extensive DUV multiple patterning.
- Overlay budget: the allowed placement error relative to neighboring layers.
- Process maturity: a well-understood DUV flow may be preferable for layers that do not need EUV resolution.
- Throughput and availability: the fab must meet production demand with predictable uptime.
- Defect and yield targets: the chosen flow must produce enough good dies to justify its complexity.
- Design rules: the chip layout and permitted pattern shapes constrain which exposure strategy is practical.
This division of labor explains why DUV shipments and installed systems remain substantial even as EUV attracts attention for leading-edge logic and memory. EUV handles the hardest layers; DUV continues to perform a large share of the total patterning work.
What “essential” means in practical terms
Calling ASML’s lithography machines essential does not mean every semiconductor process needs EUV or that ASML supplies every tool in a fab. It means that successful advanced-chip manufacturing requires a lithography capability with sufficient resolution, overlay, focus control, throughput and defect performance. EUV provides that capability for the most intricate layers at the leading edge, while DUV and the surrounding software and measurement systems support the rest of the process.
If the exposure pattern is wrong, later etch and implantation steps faithfully reproduce the wrong geometry. If layers are misaligned, transistors and interconnects can fail even when each individual layer looks acceptable. If defects are not detected quickly, a problem can consume an entire wafer lot. Lithography therefore sits at the point where design intent becomes physical structure, and its errors propagate through everything that follows.
Bottom line
ASML makes the lithography hardware and the surrounding software, metrology, inspection and service systems that let chipmakers print and control microscopic patterns. EUV’s 13.5-nanometer light and high-NA development address the tightest leading-edge layers; DUV remains indispensable for many other layers and nodes. The strategic importance comes from the integrated system’s ability to image patterns, align them across repeated process steps, detect defects and sustain useful manufacturing yield—not from a scanner operating alone.
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