AI chips are scarce because the industry must expand an entire, tightly synchronized production system—not just wafer fabrication. Training and inference demand is consuming leading-edge logic wafers, high-bandwidth memory (HBM), advanced CoWoS packaging, substrates, testing capacity, utilities, logistics and specialist labor at the same time. If any one link is short, finished accelerators cannot ship, even when other links have spare capacity.
TSMC is central because it manufactures much of the advanced logic used in AI accelerators and provides CoWoS packaging that combines compute dies with HBM. It does not make every AI chip, and increasing wafer output alone cannot solve shortages when memory, packaging or materials remain constrained.
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The short answer: AI demand is outrunning a linked supply chain
An AI accelerator is a finished system of components and processes. A typical high-performance device requires a leading-edge compute die, one or more HBM stacks, an advanced package, substrates, printed-circuit boards, power delivery, thermal hardware and several rounds of electrical and reliability testing. Each part must be available in the right specification and pass qualification at roughly the same time.
Cloud providers and other infrastructure buyers began placing unusually large orders for accelerators and complete AI servers faster than suppliers could add qualified capacity. TSMC’s 2025 annual-report material describes robust AI and high-performance-computing demand, while its regulatory filings connect that demand with expansion of advanced process nodes, specialty technologies and advanced packaging. The result is a competition for capacity across multiple factories and suppliers rather than a single missing component.
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- Leading-edge wafers: the silicon dies that perform matrix and vector calculations.
- HBM: stacked memory providing the bandwidth modern AI workloads require.
- Advanced packaging: the interconnect and assembly technology that places those dies close together.
- Substrates, boards and materials: the electrical and mechanical infrastructure around the package.
- Test, assembly and yield: the processes that turn manufactured parts into reliable shippable products.
- Utilities and logistics: electricity, water, gases, land, transport and qualified workers.
Because these constraints are coupled, the bottleneck can move. An improvement in wafer capacity may expose a shortage of HBM; more HBM may then expose limited packaging or testing capacity.
Why more wafer capacity is not enough
A wafer is an intermediate product
Fabricating a wafer creates many duplicate dies on a silicon disc. Those dies still have to be inspected, separated, electrically connected, packaged, tested and integrated into a server board. Defects, process variation and packaging failures reduce the number of usable finished units, so nominal wafer starts do not equal accelerator shipments.
AI accelerators also tend to use very large dies and advanced process technologies. Larger dies contain more opportunities for defects, making yield—the percentage of dies that meet specifications—particularly important. A fab can be busy and technologically advanced yet still produce fewer qualified accelerator packages than an order book requires.
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AI chips compete for the same advanced manufacturing resources used by premium processors, networking silicon and other high-performance products. TrendForce reported in 2026 that both advanced packaging and 3nm capacity were tightening under AI demand. That is a market assessment, not a claim that every AI accelerator uses 3nm or that all output is allocated to one customer.
What CoWoS is and why it became a bottleneck
How the package works
CoWoS is TSMC’s name for a family of chip-on-wafer-on-substrate advanced-packaging technologies. TSMC describes the service as follows:
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“CoWoS® advanced packaging service integrates multiple system-on-chip (SoC) chips and the high-bandwidth memory (HBM) stacks to enhance HPC products with superior compute power and memory bandwidth.”
In practical terms, several compute dies and HBM stacks are mounted on or connected through a silicon interposer or comparable high-density structure, which is then attached to a package substrate. The short, wide connections deliver much more memory bandwidth than routing the same signals across a conventional board.
Why packaging limits output
Advanced packaging requires specialized interposers, bonding and assembly tools, clean-room space, inspection, thermal processing and high-speed electrical testing. The package must align many connections accurately and maintain yield across a large area. A failure in one die, memory stack or interconnect can make the complete package unusable.
JETRO has reported that advanced 2.5D and 3D packaging remained supply-constrained from 2023 onward. A 2026 U.S. House testimony also identified HBM and CoWoS as bottlenecks beyond front-end wafer fabrication. These observations explain why announcements about additional wafer capacity do not immediately translate into more complete AI accelerators.
Expansion estimates are not achieved shipments
TrendForce reported a forecast or industry plan for more than 60% CoWoS-capacity expansion by 2027. The figure should be read as an expected increase in installed capacity, not a guaranteed production result. New lines must be equipped, staffed, qualified and ramped; yields can remain below target during that process.
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Why HBM is as important as the processor die
AI workloads need exceptional memory bandwidth
Large models repeatedly move weights, activations and intermediate data between compute units and memory. Conventional memory can provide capacity, but its bandwidth and energy efficiency may not meet the needs of a high-end accelerator. HBM stacks multiple memory dies vertically and connects them to the compute package through a very wide interface, reducing the distance data must travel.
HBM creates a parallel supply constraint
An accelerator designed for a particular HBM generation and capacity cannot ship at its intended specification if qualified stacks are unavailable. HBM suppliers must produce matching dies, assemble the stacks, test them and meet demanding thermal and reliability requirements. Packaging providers must then integrate those stacks with the logic dies.
This creates two failure points: an HBM shortage can hold back a package that already has a finished processor, and limited CoWoS capacity can hold back HBM that is ready to use. The finished product is constrained by whichever link has the least qualified capacity.
The other bottlenecks behind the headline shortage
As suppliers expand the most visible components, less prominent inputs can become the next limiting factor.
| Supply-chain link | What it does | How a shortage affects AI-chip output |
|---|---|---|
| ABF substrates | Provide the fine electrical routing and mechanical base beneath advanced packages. | A completed die and HBM stack may wait for a substrate that meets size, warpage and signal-integrity requirements. |
| Silicon interposers and related materials | Route thousands of short, dense connections between compute dies and memory. | Packaging lines cannot complete units without enough qualified interposers. |
| Printed-circuit boards | Connect accelerator packages, networking devices, power systems and memory in the server. | Finished packages can accumulate while complete boards remain unavailable. |
| T-glass and other specialty materials | Support high-frequency, high-layer-count boards and package structures. | Yield, signal integrity or delivery delays can reduce usable output. |
| Testing and burn-in | Verify electrical performance, thermal behavior and reliability under load. | Devices cannot ship until they pass; scarce testers or technicians create queues. |
| Solid-state storage and server components | Provide the local storage and infrastructure surrounding the accelerator. | A server may be incomplete even when its accelerator package is available. |
| Electricity, water and industrial gases | Run fabs, packaging plants and test operations. | Local utility limits or disruption can restrict production regardless of equipment installed. |
TrendForce identified tightening in several of these areas, including HBM, substrates, printed-circuit boards, T-glass and solid-state-drive-related supply chains. This is why “build more fabs” is incomplete advice: dependent suppliers must scale and qualify their inputs in parallel.
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Why TSMC matters so much—and what it does not mean
A concentrated advanced-manufacturing ecosystem
TSMC is a leading contract manufacturer for advanced logic and a major provider of CoWoS packaging. Its concentration of process expertise, equipment, suppliers and engineering talent makes Taiwan a critical node in the AI-hardware chain. Customers can design chips while relying on TSMC to fabricate them, but they still depend on TSMC’s available wafer, packaging and testing capacity.
TSMC reported research-and-development expenditure equal to 6.5% of revenue in its 2025 annual-report material. That company-reported ratio indicates sustained investment in process and packaging technology; it is not a direct measurement of how many additional accelerators the market receives.
Not every AI chip is made by TSMC
AI hardware uses multiple foundries, memory manufacturers, packaging contractors, substrate suppliers and assembly providers. Some products use different process nodes or packaging approaches. TSMC’s importance reflects its role in a large portion of the highest-performance ecosystem, not exclusive control of every AI processor.
Geographic concentration brings both efficiency and risk
Locating advanced fabs, packaging, materials suppliers and engineering teams close together improves coordination and shortens feedback loops. It also concentrates exposure to earthquakes, water or power interruptions, shipping disruptions, export controls and geopolitical instability. TSMC lists water, electricity, gases, materials, land, climate, regulation and geopolitical conditions among operational and supply-chain risks.
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Semiconductor capacity does not appear when a company announces an investment. A typical expansion involves:
- Site and utility preparation: secure land, power, water, wastewater treatment and industrial-gas connections.
- Construction: build clean rooms and supporting facilities to stringent vibration, temperature and contamination standards.
- Equipment installation: deliver and integrate lithography, deposition, etch, metrology, packaging and test tools.
- Process qualification: run wafers and packages, tune recipes, measure defects and establish reliable yields.
- Customer qualification: prove that a specific design, memory stack and package meet electrical and reliability requirements.
- Ramp: increase volume while maintaining yield, worker training, maintenance and supply continuity.
Packaging and HBM capacity follow similar paths. A line can be physically complete but commercially constrained until customers approve its output. This lag lets demand stay ahead even while new factories and packaging halls are visibly under construction.
When will AI-chip shortages end?
No defensible single end date has been established. The answer depends on whether demand growth slows, whether suppliers add capacity faster than orders increase, and which component becomes the next constraint.
Conditions that would ease shortages
- Cloud and enterprise buyers moderate new accelerator orders or improve utilization of installed systems.
- Leading-edge wafer yields improve, increasing usable dies from the same wafer starts.
- HBM manufacturers add qualified stacks and transition smoothly to newer generations.
- CoWoS and competing advanced-packaging lines ramp with acceptable yields.
- Substrate, board, test and utility suppliers expand alongside fabs.
- Geopolitical or logistics disruptions do not remove newly added capacity.
Why relief may arrive unevenly
Supply can improve for one accelerator model while another remains constrained by a different memory configuration, package size or process node. Large cloud customers with long-term allocations may receive products before smaller buyers. A reported capacity increase may also be absorbed by additional demand instead of creating visible availability in every market.
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1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minuteHow to read claims about the shortage
Separate three kinds of statements when evaluating an announcement:
- Announced plan: a company says it intends to build or equip capacity. This is not operating output.
- Market forecast: an analyst estimates future capacity, demand or constraints. The TrendForce figure of more than 60% CoWoS expansion by 2027 belongs in this category.
- Achieved output: audited or operational data showing qualified units shipped. This is the strongest evidence that supply has actually increased.
Also ask which layer the statement covers. “More wafers” says little about HBM allocation, package availability, substrate supply or final server assembly. A credible assessment identifies the process node, package type, memory generation, qualification status, geography and measurement date.
What this means for the AI hardware market
Shortages favor buyers able to commit early, accept multiple configurations or negotiate long-term supply agreements. Smaller organizations may face longer lead times because allocation is tied to complete systems, not just a processor on a shelf. System designers increasingly consider alternative package sizes, memory configurations, process nodes and accelerator architectures to avoid relying on one constrained path.
For policymakers and infrastructure planners, resilience requires more than replicating a leading-edge fab. It includes domestic or diversified packaging, HBM and substrate capacity, trained workers, reliable power and water, secure transport and coordinated export-control policy. Diversification can reduce single-region exposure, but duplicating every specialty process is expensive and cannot be completed quickly.
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The practical takeaway
AI-chip shortages are best understood as a synchronization problem. Leading-edge silicon is necessary, but a shippable accelerator also needs HBM, high-density packaging, substrates, testing, utilities and logistics. TSMC’s manufacturing and CoWoS role makes it a pivotal part of the chain, while Taiwan’s concentrated ecosystem increases both efficiency and exposure. New capacity should gradually help, yet construction, qualification and ramping take years, and the binding constraint can shift before the market reaches balance.
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