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What Volantis means by the “memory wall”
AI inference needs to move model weights and other data between memory and compute quickly. If memory cannot supply data fast enough, adding more compute does not necessarily make a system serve each request faster. That mismatch is often called the memory wall.
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Memory choices involve a trade-off. SRAM located on a processor can provide high bandwidth, but its capacity is limited. High-bandwidth memory (HBM) can provide more capacity, yet bandwidth remains a constraint. Volantis argues that moving memory farther from the compute die over conventional short-reach electrical connections can make it harder to preserve bandwidth.
How A-1 is intended to address it
Volantis’s proposal is to use an optical fabric and a photonic interposer to connect compute and pooled off-chip memory. In principle, optical links could carry data over a greater distance than short-reach electrical links while maintaining high bandwidth. That could let a system use more memory without the same bandwidth penalty, according to the company’s design thesis.
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This is a photonic interconnect proposal, not a claim that A-1 performs inference using optical computing. Volantis says its fabric uses custom integrated micro-VCSELs and optical connections that differ from conventional fiber-based approaches. Those are descriptions of the planned design, not independently verified product characteristics.
The Register reported that A-1 is meant to focus Volantis’s work on the optical interposer, with the company licensing other intellectual property. The specific memory technology A-1 will use has not been disclosed in that reporting.
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What Volantis has announced—and what the figures mean
The figures below describe company targets or claims, not a common benchmark. They come from different announcements and reports, and should not be treated as results from one tested system.
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| Figure | What it refers to | Source and qualification |
|---|---|---|
| More than 10 TB of memory; up to 240 TB/s | A-1’s intended memory capacity and bandwidth | The Register, Oct. 5, 2026, reporting Volantis’s aims; not measured results. |
| Models exceeding 20 trillion parameters; up to 10,000 tokens per second per user | System design targets | Volantis via PR Newswire, Oct. 1, 2026; not an independently validated throughput result. |
| 1 picojoule per bit per 24 Gbps lane; about 20 kW total system power | Intended link energy and system power | The Register, Oct. 5, 2026, reporting targets; neither figure is a measured product result. |
| 12 to 18 months | Target timeline to a working prototype | The Register, Oct. 5, 2026; this is a prototype target, not a volume-production schedule. |
| More than 30× bandwidth; more than 50× memory size | Performance claims displayed on Volantis’s homepage | Company marketing claims; the cited material does not establish independent measurements or specify comparison baselines. |
Volantis’s funding figures also refer to separate dates and measures. The company said on Sept. 29, 2026, that it had raised $97 million to date. On Oct. 1, 2026, it separately announced an $88 million Series A co-led by Lachy Groom and Abstract Ventures. Those amounts should not be conflated. The named co-leads in that announcement do not, by themselves, establish the separate “Altman-backed” characterization sometimes attached to the company.
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Why the design is ambitious—and what remains unproven
The central engineering challenge is not simply to connect memory optically. A usable accelerator would need the optical interposer, compute, memory, packaging, control systems and software to work together at scale. The Register described Volantis as needing to move from small optical demonstrators toward a product-like system and integrate licensed IP.
The reports and announcements available as of Oct. 7, 2026, do not establish a working A-1 prototype or independently validate its advertised throughput, power, memory capacity or supported model size. They also do not establish A-1’s memory supplier, production partners, selected memory type, measured performance or production date. The planned prototype timeline therefore should not be read as evidence that a commercial system is imminent.
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Power efficiency is another open question. The energy-per-bit and total-system-power figures are targets, and a link-level energy figure alone cannot show how efficient a complete inference system would be. A meaningful evaluation would need comparable measurements for sustained bandwidth, latency, total power, cost per token, software and IP integration, and maturity—from demonstrator to prototype to production—against GPUs, TPUs and other interconnect approaches. The available figures do not provide that comparison.
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