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Both companies reported first-generation 2nm production in the fourth quarter of 2025. The “2nm” labels are not proof that the processes are equivalent: the available sources do not provide matched third-party measurements of density, performance, power, yield, defect rates, wafer cost or customer volume. The practical comparison therefore rests on five questions: what is actually in production, how each business is structured and measured, where capacity is located, what customer ecosystem evidence exists, and what each company says it will do next.
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The short answer: different strengths, incomplete like-for-like data
TSMC and Samsung Foundry compete for many of the same leading-edge and specialty manufacturing programs, but they are not reported as equivalent businesses. TSMC is a pure-play foundry: it manufactures customers’ designs and says it does not design, manufacture or market semiconductor products under its own name. Samsung Foundry is a business unit of Samsung Electronics, alongside System LSI, memory and other semiconductor operations. Samsung promotes integrated logic, memory and advanced-packaging solutions, which can be strategically valuable but makes the foundry segment harder to isolate financially.
On confirmed production, TSMC says its N2 process entered high-volume manufacturing in the fourth quarter of 2025. Samsung says its Foundry Business began mass production of first-generation 2nm products in the same quarter. Those statements establish company-reported production milestones, not a head-to-head process victory. TSMC’s disclosures are much richer on revenue, shipments, customers, technologies and capacity. Samsung’s cited FY2025 release emphasizes milestones, growth goals and integrated offerings rather than a separate operating statement.
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For a chip designer choosing a foundry, the answer depends on the product and location requirements. TSMC presents a broad, independently focused manufacturing network with extensive reported customer and process breadth. Samsung presents a vertically integrated platform that links logic, memory and packaging and is expanding its 2nm offering. Neither company’s node number alone tells you which will deliver the better cost, yield or schedule for a particular design.
How the two foundry businesses are organized
TSMC’s pure-play model
TSMC describes its model as “pure play,” meaning it focuses on manufacturing semiconductor products designed by customers rather than selling chips of its own design. In its 2025 Annual Report, chairman and chief executive C.C. Wei wrote that the company’s “biggest responsibility is to support our customers with the most advanced technologies and necessary capacity to unleash their innovations.” He also said, “Our success is predicated on our steadfast adherence to the pure-play foundry business model.”
This structure is intended to reduce the concern that a manufacturer might compete with customers using their designs or market knowledge. TSMC’s offering spans leading-edge logic, specialty processes and advanced packaging. Its reported customer count and product totals cover the company’s manufacturing activity rather than a separately carved-out “foundry” subsidiary.
Samsung Foundry inside Samsung Electronics
Samsung Foundry operates within Samsung Electronics’ wider semiconductor organization. The company discusses Foundry alongside System LSI and other businesses, and its strategy combines logic manufacturing with Samsung’s memory expertise and advanced packaging. That arrangement can support an integrated solution—for example, coordinating logic, high-bandwidth-memory base dies and packaging—but it also means public financial results do not isolate Foundry in the same way TSMC reports its company-wide manufacturing business.
Samsung’s SAFE (Samsung Advanced Foundry Ecosystem) program is the surrounding design and enablement network. The company has announced a design-platform collaboration with Cadence for its 2nm process and expanded memory-and-foundry collaboration with Broadcom. These announcements demonstrate ecosystem activity; they do not establish a comparable total partner count or prove that one ecosystem has better yields or customer satisfaction.
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Process technology: what is in production and what remains a roadmap
TSMC’s reported nodes
TSMC’s 2025 Annual Report states that N2 entered high-volume manufacturing in the fourth quarter of 2025, with a fast ramp expected in 2026. The report scheduled N2P and A16 volume production for the second half of 2026 and A14 for 2028. These are the company’s status statements and schedules as of the report; they should not be read as independent confirmation of customer yields or delivery volumes.
TSMC describes A16’s Super Power Rail as suited to some high-performance-computing products with complex signal routes and dense power-delivery networks. That is a product-positioning and technical description from TSMC, not a published comparison against Samsung’s equivalent process. A roadmap date also does not guarantee that every customer can tape out or receive wafers on that date.
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Samsung’s reported nodes
Samsung’s FY2025 results say the Foundry Business commenced mass production of first-generation 2nm products in the fourth quarter of 2025 and began shipments of 4nm HBM base-die products. Samsung’s current logic-node page labels SF2 mass production as started in 2025, SF3 in 2022, SF4 in 2021 and SF5 in 2021.
Samsung describes SF2 as second-generation MBCFET gate-all-around technology for mobile, high-performance-computing, artificial-intelligence and automotive applications. Its company information describes SF2Z for HPC and AI and SF2A for automotive as planned uses. “Planned” identifies a roadmap application, not completed production. Samsung also says it intends to ramp second-generation 2nm products; that is a target, not evidence that the ramp has already occurred.
Why “2nm versus 2nm” is not a benchmark
Process names are company-specific labels. The sources available for this comparison do not provide a matched, independent test of transistor density, operating performance, power at a defined workload, defect density, yield, wafer price or customer production volume for TSMC N2 and Samsung SF2. Gate-all-around terminology, backside or power-delivery features and packaging choices can affect a finished product, but a node name cannot reduce those variables to one ranking.
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When evaluating a real program, request the foundry’s process design kit, design-rule documentation, reliability data, expected wafer sort and final-test flows, package options, capacity reservation terms and production-yield history for the relevant product class. Compare like-for-like workloads and package configurations, and label every performance or schedule claim by the company that made it.
Scale and financial disclosure
TSMC publishes a detailed company-wide operating picture. Samsung’s cited release does not publish an equivalent standalone Foundry statement. The following table keeps the measures separate rather than manufacturing a false like-for-like ranking.
| Measure | TSMC (2025) | Samsung Foundry (FY2025 release) | How to interpret it |
|---|---|---|---|
| Reported revenue | US$122.42 billion consolidated revenue | Standalone Foundry revenue not stated | TSMC’s figure covers the consolidated company; it is not a Foundry-only number to compare with Samsung. |
| Net income | US$55.21 billion consolidated net income | Standalone Foundry net income not stated | Different reporting scopes prevent a segment-margin comparison. |
| Year-over-year revenue growth | 35.9% in U.S.-dollar terms versus 2024 | Foundry target of double-digit revenue growth in 2026 | TSMC’s figure is a reported 2025 result; Samsung’s is a forward target. |
| 12-inch-equivalent wafer shipments | 15.0 million, up from 12.9 million in 2024 | Not stated | Shipments are different from installed or potential capacity. |
| Advanced-process mix | 74% of wafer revenue from 7nm-and-more-advanced technologies; 3nm was 24% of total wafer revenue in its third full volume-ramp year | Not stated on a comparable revenue basis | TSMC’s percentages refer to wafer revenue, not all company revenue or physical wafers. |
| Process technologies, products and customers | 305 process technologies, 12,682 products and 534 customers | Comparable totals not stated | These are TSMC’s annual company-reported totals, not market-share estimates. |
| Annual manufacturing capacity | More than 17 million 12-inch-equivalent wafers | Not stated in the cited release | Capacity is a potential output measure; it is not the same as actual shipments. |
TSMC reported that consolidated revenue grew 35.9% in U.S.-dollar terms in 2025. It shipped 15.0 million 12-inch-equivalent wafers, compared with 12.9 million in 2024. The company’s 74% advanced-technology wafer-revenue share and 3nm share are mix indicators, not direct measures of transistor leadership. Samsung’s absence of a Foundry revenue or shipment figure in the cited FY2025 announcement does not prove that no other filing or dataset contains such a number; it means this source does not provide a clean comparison.
Manufacturing footprint and capacity plans
TSMC’s existing and planned sites
TSMC’s reported capacity spans fabs and operations in Taiwan, Nanjing, Arizona, Japan and a China subsidiary. Its fundamentals information lists more than 17 million 12-inch-equivalent wafers of annual manufacturing capacity. A specialty-technology fab in Germany is under construction and aimed at automotive and industrial applications.
The company’s 2025 Annual Report says its first Arizona fab entered high-volume production in the fourth quarter of 2024. It expects the second Arizona fab to enter high-volume manufacturing in the second half of 2027, and says construction of a third began in 2025. A second Japan fab is under construction, with planned 3nm production there. “Under construction,” “planned” and “expected” describe projects or schedules, not capacity already available to customers.
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Samsung’s integrated capacity story
The cited Samsung materials emphasize process milestones, integrated logic-memory-packaging capability and the expansion of advanced nodes rather than a site-by-site wafer-capacity total. Samsung’s 4nm HBM base-die shipments show how its foundry and memory businesses can intersect. That is strategically different from a pure-play model, but the available figures do not support calculating Samsung Foundry’s installed capacity or comparing it numerically with TSMC’s 17-million-plus figure.
For a location-sensitive program, ask both suppliers which specific fab will run the wafer, whether the process is qualified there, how much capacity is reserved, what export or regional rules apply, and when packaging and test capacity becomes available. A company-wide capacity headline cannot answer those questions by itself.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Customers, design enablement and packaging
TSMC reports manufacturing 12,682 products for 534 customers across 305 process technologies in 2025. Those figures indicate broad customer and product reach, but they do not identify which customers use a particular node, how much volume each contributes or what each program’s yield is.
Samsung’s SAFE ecosystem is designed to provide design tools, intellectual-property support and technical enablement around Samsung processes. The announced Cadence collaboration concerns a design platform for Samsung’s 2nm process. Samsung has also announced expanded memory and foundry collaboration with Broadcom. These are named examples of ecosystem work, not evidence of a larger or smaller total ecosystem than TSMC’s.
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Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstallAdvanced packaging is increasingly part of the manufacturing decision. TSMC describes advanced packaging as part of its foundry portfolio. Samsung promotes integrated logic, memory and advanced packaging, including its relationship to HBM base-die production. A customer should compare package technology, interposer or substrate availability, thermal limits, known-good-die flows, test coverage and lead times—not just front-end wafer nodes.
Which company is more advanced?
There is no defensible single answer from the reported evidence. Both companies claim first-generation 2nm production in the fourth quarter of 2025. TSMC reports N2 high-volume manufacturing and a roadmap including N2P, A16 and A14; Samsung reports SF2 mass production, SF2’s MBCFET gate-all-around design and planned SF2Z and SF2A variants. The sources do not establish equivalent density, power, performance, yield or cost.
If “advanced” means breadth of publicly reported manufacturing scale and customer coverage, TSMC provides stronger evidence: 534 customers, 12,682 products, 305 technologies, 15.0 million wafer shipments and more than 17 million wafers of annual capacity. If it means an integrated logic-memory-packaging proposition, Samsung’s organizational model is distinctive. Neither interpretation is a substitute for a product-specific qualification and commercial comparison.
Outlook for 2026 and beyond
TSMC’s stated outlook
TSMC says AI-related demand should remain robust entering 2026, while acknowledging macroeconomic uncertainty. Management expects its leading-edge, specialty and advanced-packaging technologies to support growth faster than the overall industry. That is management’s outlook, not a guaranteed result. The N2 ramp, scheduled N2P and A16 production in the second half of 2026, and A14 target for 2028 are milestones to monitor.
Samsung’s stated outlook
Samsung’s FY2025 announcement says its 2026 Foundry target is double-digit revenue growth and improved profitability, driven by advanced nodes. It also says the business plans to ramp second-generation 2nm products and strengthen integrated logic, memory and advanced-packaging solutions. These are corporate targets and plans; they are not reported results or independent forecasts.
A practical decision framework for chip designers
- Define the product requirement. Set the performance, power, die-size, package, automotive or consumer qualification, production volume and launch-date requirements before comparing node names.
- Confirm production status. Ask whether the exact process variant is in high-volume or mass production at the fab that would run your wafers. Do not treat a roadmap designation such as SF2A, SF2Z, A16 or A14 as current production without written confirmation.
- Compare design enablement. Review the process-design kit release, supported electronic-design-automation flows, intellectual-property libraries, standard-cell options, analog and radio-frequency offerings, memory compilers and sign-off requirements.
- Request comparable manufacturing data. For the same design class, obtain expected yield-learning curves, defect-density assumptions, wafer costs, cycle times, reticle limits, reliability qualifications and engineering-lot schedules. Keep company claims labeled as claims until validated under a mutual non-disclosure agreement.
- Check packaging and memory dependencies. Evaluate 2.5D or 3D integration, HBM access, substrates, interposers, thermal design, test and final-assembly capacity. A faster transistor process can lose its system advantage if packaging is constrained.
- Map geographic and continuity needs. Identify the qualifying fab, backup fab, cross-border logistics, export-control exposure and disaster-recovery plan. Existing Arizona, Japan and Taiwan capacity is different from projects scheduled for future years.
- Model the commercial commitment. Compare non-recurring engineering charges, mask costs, wafer pricing, capacity reservations, minimum volumes, change-control rules and end-of-life policies. Public annual reports cannot answer these contract-specific questions.
- Run a full-product benchmark. Measure the finished chip and package on the intended workload. Do not infer system performance from “2nm,” gate-all-around terminology or a marketing claim about a power rail.
Common mistakes when comparing TSMC and Samsung Foundry
- Ranking by node number alone: “2nm” is a label, not a universal specification.
- Comparing consolidated TSMC revenue with an invented Samsung Foundry number: Samsung’s cited release does not provide a standalone figure.
- Confusing capacity with shipments: TSMC’s more-than-17-million capacity and 15.0-million shipments measure different things.
- Counting roadmaps as factories: planned nodes, fabs and applications may change before qualification or volume output.
- Turning partner announcements into ecosystem rankings: Cadence and Broadcom collaborations establish activity, not a total partner count or performance ranking.
- Assuming a company-wide number describes one node: TSMC’s customers, products, technologies and revenue figures span its portfolio.
- Ignoring packaging: Logic, memory, interconnect and test can determine system cost and performance as much as the front-end process.
What the public evidence can and cannot establish
The evidence establishes that both companies reported leading-edge 2nm production in late 2025; that TSMC supplies substantially more detailed company-wide manufacturing and financial statistics; that Samsung combines foundry with memory and packaging capabilities; and that both have active next-generation roadmaps. It does not establish a neutral winner on yield, transistor density, performance per watt, cost, customer satisfaction, market share or production volume for a specific chip.
Those limits matter because foundry selection is a program decision, not a league table. A design may favor TSMC’s reported breadth and pure-play separation, Samsung’s integrated memory and packaging proposition, a particular geographic site, or a process variant that is better qualified for its workload. The responsible comparison is therefore the one that starts with verified production status and ends with measured product results.
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