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Emitter-Coupled Logic (ECL) is a high-speed bipolar logic family that represents a bit by steering an approximately constant current between branches of a transistor differential pair. The switching transistors stay out of deep saturation, so they avoid stored-charge delay and can change state very quickly. That speed comes with continuous current, carefully specified voltage levels, transmission-line termination and more demanding layout than ordinary CMOS.
What “emitter-coupled” means
In the basic circuit, the emitters of two bipolar junction transistors are joined to a shared current source or sink. This is the classic long-tailed differential pair. A reference voltage is applied to one base and a logic input (or inputs) to the other. The shared tail current is redistributed according to the difference between the base voltages; the circuit does not independently switch each emitter current.
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A simplified conceptual gate looks like this:
VCC
|
collector loads
| |
Q1 Q2
/
/
+------+
|
constant-current
source/sink
|
VEE
input and reference voltages drive the two bases
Real devices add bias networks, multiple input transistors, output buffers and protection structures. The diagram explains the operating principle, not a copy-ready manufacturer schematic.
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The tail source supplies nearly constant current. If the positive-input transistor’s base is higher than the other base, it takes most of that current and the opposite branch takes less. Reversing the input relationship steers the current to the other collector. Near equality, current divides and the circuit is in its transition region.
| Differential input relationship | Current mainly flows through | Result |
|---|---|---|
| VIN+ > VIN− | Positive-input transistor | One complementary output state |
| VIN− > VIN+ | Negative-input transistor | Opposite complementary output state |
| Inputs nearly equal | Current divides | Transition or metastable region |
The non-selected transistor is not necessarily at exactly zero current; residual current and the switching threshold depend on the device’s bias and transistor design. ECL is therefore better understood as controlled current redirection than as ideal one-transistor-on/one-transistor-off logic.
Why ECL is fast
Switching without deep saturation
A saturated BJT stores charge. Removing that charge delays turn-off, which limits saturated transistor logic. ECL limits the voltage conditions so its switching transistors remain in the active region, avoiding most of that storage delay. Microchip describes this saturation avoidance as a central reason for ECL’s speed (Microchip ECL documentation).
Small voltage movement
Charging a line or package capacitance through a large voltage range takes more charge and time. TI’s interface discussion gives approximately 800 mV as a typical ECL output swing and about 1.6 V peak-to-peak for a differential pair, depending on how the swing is defined (TI SLLA067). These are typical figures, not universal guarantees; use the selected device’s VIH, VIL, VOH, VOL, differential-amplitude and common-mode specifications.
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Classic ECL commonly uses emitter-follower outputs. Their low output impedance and transistor-junction level shift suit controlled-impedance lines and resistive loads. They do not produce rail-to-rail CMOS levels: the output sits an approximately junction-voltage offset from the relevant supply and must be used with its specified receiver and termination (ON Semiconductor AND8066/D).
Voltage swing, polarity and common-mode voltage
Three different quantities are often confused:
- Single-ended swing: the change on one output measured against a reference.
- Differential swing: the voltage difference between true and complementary outputs.
- Common-mode voltage: the average of the two output voltages.
A receiver can have adequate differential amplitude while still violating its common-mode range. Logic polarity is also not universal: which output is called “true” depends on the device truth table and whether the system uses positive or negative logic conventions.
Classic negative-supply ECL commonly places VCC near 0 V and uses VEE around −5.2 V. Positive ECL (PECL) uses positive rails, commonly 5 V and ground; LVPECL uses lower positive supplies such as 3.3 V or 2.5 V. Exact allowable rails and levels are part-specific (TI SLLA067; Analog Devices PECL overview).
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ECL, NECL, PECL and LVPECL
| Name | Meaning | Typical supply orientation | Important qualification |
|---|---|---|---|
| ECL | Broad family name, often used for classic negative ECL | VCC near 0 V; negative VEE | Confirm the exact device convention |
| NECL | Negative ECL | Negative supply | Polarity is made explicit by the name |
| PECL | Positive ECL | Positive VCC, ground return | Not automatically pin- or voltage-compatible with every ECL part |
| LVPECL | Low-voltage PECL | Commonly 3.3 V or 2.5 V | Input range, swing and termination still vary |
| ECLinPS and similar names | Manufacturer product-family branding | Datasheet-specific | The family name does not replace electrical specifications |
Before connecting any two parts, check supply voltage, input common-mode range, differential input amplitude, output levels, termination voltage, internal biasing and whether AC coupling is allowed. “PECL-compatible” is not a blanket promise of LVPECL compatibility.
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A single reference branch can be compared with one or several input branches. Multiple transistors let the highest or lowest input control current steering, depending on the topology. The two output branches naturally provide a function and its complement, so an ECL gate can supply OR/NOR-like or AND/NAND-like behavior without a separate inverter. The exact truth-table polarity depends on the input arrangement and on which output is designated true; consult the device truth table rather than assuming a universal “ECL NAND.”
Termination is part of the circuit
At ECL edge rates, a PCB trace is often a transmission line. A common interface uses controlled impedance and a 50-Ω parallel termination at the receiver, but the resistor must connect to the voltage and topology specified for that output structure. Classic negative ECL may terminate toward VEE; PECL arrangements often use VCC−2 V or a named VTT/VTERM rail. Some modern current-mode outputs integrate approximately 50-Ω structures or use CML-style back termination (TI SLCA006; ON Semiconductor AND8173/D).
- Identify the output circuit in the datasheet: emitter follower, integrated termination or CML-like output.
- Read the recommended receiver network and termination voltage; do not infer it from “50 Ω” alone.
- Place termination where the datasheet specifies, usually at the receiving end for a parallel-terminated line.
- Terminate both members of a differential pair when required, even if only one output is used; some fanout devices explicitly require this.
- Verify the resulting DC current, voltage compliance and power in the termination rail.
Never copy a generic 50-Ω ECL circuit from another part. The same resistor value can be correct for one family and wrong for another.
Differential routing and measurement
- Route the pair with controlled impedance, close spacing and the required length match.
- Maintain a continuous reference and return-current path; avoid stubs, unnecessary vias and abrupt discontinuities.
- Place termination and decoupling components close to the locations specified by the datasheet.
- Treat the termination supply as a high-speed node and decouple every supply rail locally.
- Use a high-bandwidth differential probe or a properly terminated coaxial setup. A long oscilloscope ground lead can create ringing that is not present in the circuit.
Differential signaling rejects noise common to both traces and reduces sensitivity to ground-potential differences, but it is not immune to poor return paths, skew, supply noise or incorrect common-mode bias (TI differential-signal-integrity guidance).
Power and noise trade-offs
The tail current flows even when the logic state is not changing. Output termination can also draw current continuously, and low-value resistors dissipate power. TI identifies these continuously active structures and termination resistors as major reasons ECL has high power dissipation (TI SLCA006).
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Unlike CMOS, whose dynamic power usually rises strongly with switching frequency, ECL power is comparatively steady with activity. That does not make ECL low-power; it changes the power-versus-frequency trade-off. Differential operation, small swings and controlled current paths can reduce supply-current transients and common-mode interference, but layout and termination still determine system-level noise performance.
Interfacing ECL with other logic families
CMOS and TTL
Use a dedicated translator or a verified resistor/bias network. An ECL output may be too negative, too high, or outside a CMOS/TTL input’s absolute-maximum or threshold range. Check VIH, VIL, absolute maximum voltage and common-mode limits rather than relying on the word “digital.”
LVDS
An ECL-to-LVDS connection is possible with a translator or a carefully designed AC- or DC-coupled interface. LVDS generally uses different common-mode and smaller differential-voltage requirements and is often chosen when lower power is more important than the ECL ecosystem (Analog Devices AN-1177).
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CML
CML and ECL both steer current, but their output impedance, biasing, voltage levels and termination differ. Emitter-follower ECL should not be treated as interchangeable with a 50-Ω CML output (ON Semiconductor AND8173/D).
AC coupling
AC coupling can shift a signal between standards only when the receiving side supplies the correct DC bias and can tolerate the signal’s low-frequency content. It is not a universal fix for incompatible levels or arbitrary data patterns (Analog Devices AC-coupling discussion).
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Unused inputs and outputs
Never leave an unused input open unless the datasheet explicitly defines that condition. Bias it to a valid state using the manufacturer’s recommended connection. Some parts include input pulldowns; for example, ON Semiconductor’s MC10EL11/MC100EL11 documentation describes internal pulldowns and a defined low-output condition when inputs are open or tied to VEE (MC10EL11/MC100EL11 datasheet). That behavior must not be generalized to other parts.
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Unused complementary outputs may still need termination, particularly in clock fanout devices. Follow the output-loading recommendations for the exact package and operating mode.
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When ECL is a good choice
- Very low propagation delay or multi-gigahertz clock/data distribution is required.
- The system already uses PECL or LVPECL receivers, termination rails and controlled-impedance routing.
- Complementary outputs, low skew and differential transmission are valuable.
- Continuous current and the associated thermal budget are acceptable.
When to choose something else
- Lowest power, simple local control logic or direct CMOS interoperability dominates.
- The board cannot provide the required termination and bias rails.
- The team cannot support high-speed layout and measurement.
- Long-term supply is critical but the candidate ECL family is legacy or obsolete.
LVDS is often a lower-power board-level alternative; CML suits systems already built around 50-Ω current-mode serial links; modern CMOS is usually simpler for local logic. The right choice depends on speed, jitter, reach, voltage, power, receiver ecosystem and lifecycle.
Availability and example devices
ECL remains relevant in clock distribution, timing, telecommunications, instrumentation and point-to-point links, but product status is uneven. For example, ON Semiconductor documents the MC10EL11/MC100EL11 as a differential 1:2 buffer with typical 265-ps propagation delay and 5-ps output skew, while the MC10EP11/MC100EP11 is documented as a 3.3-V/5-V ECL 1:2 buffer with typical 220-ps propagation delay; ordering options and lifecycle status must be checked in the current datasheets (MC10EL11/MC100EL11; MC10EP11/MC100EP11).
Renesas lists MC100ES6011 and MC100ES6221 fanout products for lower-voltage ECL/PECL systems, but its pages mark those examples obsolete and direct users toward authorized-distributor or portfolio-transition information (MC100ES6011; MC100ES6221). A historical datasheet or distributor listing is not proof of continuing production. For a new design, verify lifecycle status, package, authorized stock, minimum order quantity and the complete termination network before committing.
Design and debug checklist
- Confirm whether the part is NECL, PECL, LVPECL or CML-like and record all supply rails.
- Check input common-mode range, differential amplitude, logic polarity and absolute maximum ratings.
- Use the manufacturer’s termination voltage and topology, not a generic ground-connected 50-Ω resistor.
- Terminate both differential outputs when required.
- Bias every unused input as specified and load unused outputs as recommended.
- Route differential traces with controlled impedance, matched delay and a continuous return path.
- Place local supply and termination-rail decoupling at the device.
- Measure with a differential probe or correctly terminated coaxial fixture.
- Investigate wrong polarity, common-mode error, unterminated lines, floating inputs and probe-induced ringing before blaming the logic core.
The Bottom Line
ECL is fast because it steers a nearly constant current through a differential BJT pair without driving the transistors into saturation. Its practical performance depends just as much on the correct supply orientation, common-mode range, termination, routing and lifecycle-appropriate part selection as on the transistor circuit itself.
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