Yes: a CPU can make a later load visible before an earlier store to a different address is visible to another core. The standard “both reads return zero” store-buffering outcome is allowed on both x86 and ARM64, though the architectures permit different sets of memory-operation reorderings. Intel’s documentation on speculative store bypass describes a separate transient-execution security issue; it does not show that Intel hid ordinary store-to-load reordering.
What store-to-load reordering means
Consider two shared variables, initially zero, and two threads:
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Thread 1 Thread 2
X = 1; Y = 1;
r1 = Y; r2 = X;If both loads return zero, each thread has read the other variable before seeing the other thread’s store. A globally sequentially consistent order that preserves each thread’s store-before-load sequence cannot produce that result: whichever store came first would have to be visible to the other thread’s later load. Store buffers can allow each core’s load to proceed while its earlier store to a different address is still pending from the other core’s perspective.
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Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →Scan for outdated or missing drivers - takes under a minuteDriver Scan →This is the store-buffering litmus test. Its both-zero result is permitted by both x86 TSO and Arm’s weaker memory model. A result being uncommon in a short run does not make it impossible. Harrison Guo’s explanation and test uses this example.
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Which access pairs can be reordered?
Arm’s comparison of the four basic load/store pairings gives the following architectural picture:
| Earlier operation → later operation | x86 | Arm |
|---|---|---|
| Load → Load | Reordering not allowed | Reordering allowed |
| Load → Store | Reordering not allowed | Reordering allowed |
| Store → Store | Reordering not allowed | Reordering allowed |
| Store → Load | Reordering allowed | Reordering allowed |
This is an architecture-level comparison, not a complete recipe for writing concurrent programs. The permitted behavior of a program also depends on its programming language’s memory model, compiler, and synchronization protocol. A data race or inadequate synchronization is not made correct simply because it appears to work on a more strongly ordered processor. Arm Community’s DPDK guidance describes these ordering distinctions.
Why code that works on x86 can fail on ARM64
“It works on our Intel CI and on the developers’ older MacBooks, but it corrupts data, deadlocks, or returns impossible values on Graviton” is a useful way to describe a migration symptom—not proof that ARM64 is malfunctioning. x86 disallows three of the four reorderings in Arm’s comparison that Arm permits, so code relying on accidental ordering can be exposed when moved to Arm64.
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The processor is only one layer. Compilers may transform code within the rules of the source language, and each language defines what concurrent accesses and atomic operations guarantee. The sources cited here establish the architecture comparison but do not support detailed, language-specific claims for C, C++, Rust, or Go. For a real fix, consult the relevant language’s authoritative concurrency documentation and express the required communication using its supported atomics and synchronization primitives.
What the reported test numbers do—and do not—show
Guo reports approximately 2.3% both-zero outcomes in one million iterations without barriers and approximately 1.8% in one million iterations with a compiler barrier only. In the same test setup, the author reports zero observed both-zero outcomes when each thread used a full barrier. These are author-reported results from a particular test, not universal rates for x86 or ARM64, nor a guarantee that a full barrier repairs an arbitrary production program. A repost of the article carries an author comment reiterating the no-barrier and full-barrier figures; it is not an independent replication. The repost and comment provide that clarification.
A compiler barrier and a CPU memory barrier address different layers. The compiler-only case is intended to prevent compiler movement of memory references; it does not, by itself, constrain hardware ordering. Likewise, volatile is not a general-purpose concurrency synchronization mechanism. Use the language’s atomic and synchronization facilities rather than treating a compiler directive or a volatile access as a substitute.
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Choosing barriers and synchronization on Arm
Arm describes barriers as having distinct purposes and scopes. The right choice depends on which memory operations must be ordered and among which observers:
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- DMB: orders data accesses within the specified shareability domain.
- DSB: provides similar ordering while also preventing further instruction execution until synchronization completes.
- Acquire-load and release-store: Arm64 operations with implicit ordering semantics that are less restrictive than DMB or DSB.
These architecture-level descriptions do not identify the correct source-language primitive for every algorithm. Start from the algorithm’s required guarantee and use the appropriate language-level atomic or synchronization operation; do not add the strongest available fence everywhere. Arm warns that unnecessary barriers can reduce performance, and its guidance discusses cases where lighter synchronization can improve it. Arm’s DPDK optimization article gives the architecture guidance and barrier context.
What Intel’s speculative-store-bypass guidance actually says
Intel’s page, “Hardware Features and Behaviors Related to Speculative Execution”, describes a different mechanism. Many Intel processors use memory-disambiguation predictors that can let a load execute speculatively before it is known whether its address overlaps an earlier store. If an overlap is later found, the load may have transiently consumed stale data and is re-executed to preserve architectural correctness. Intel discusses mitigations including process isolation, selective LFENCE use, and Speculative Store Bypass Disable (SSBD), with possible performance effects.
That discussion concerns speculative transient execution and potential side channels. It is not evidence that Intel concealed the ordinary architectural store-buffering outcome, which is permitted on x86 as well as ARM64.
Quick Recap
How to investigate a cross-architecture concurrency bug
- Reduce the failure to a small test. Identify the shared locations, the operations on each thread, and the unexpected outcome. The store-buffering example above is a model for a minimal test, not a diagnosis for every bug.
- Check the language-level contract. Verify that the shared state is accessed through valid atomics or synchronization for the language and that the chosen ordering establishes the required communication.
- Test on the target architecture. Run lock-free and low-level concurrent code on ARM64 if ARM64 is a deployment target. Local ARM hardware is one option; an ARM cloud platform is another. Testing can reveal a bug, but does not itself make the algorithm correct.
- Use only the ordering the protocol needs. Select a suitable atomic operation or barrier scope, then evaluate correctness and performance. A strong fence in a litmus test is not a universal application fix.
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