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Choose NVIDIA when CUDA compatibility, broad framework support, custom-kernel flexibility and deployment options are your biggest constraints. Choose AMD Instinct when an open ROCm stack, high-memory accelerators or a second supply path matter—and your team can test the exact software on MI300 hardware. Choose Google TPU when the model is dominated by dense tensor operations that compile cleanly with XLA, your team is comfortable with JAX or PyTorch/XLA, and Google Cloud is an acceptable dependency.
There is no universal winner. Memory capacity, interconnect topology, compiler behavior, utilization and software porting risk often matter more than a peak-FLOPS number. The right comparison is cost per useful training step or generated token on your model, precision, batch size and parallelism—not a vendor headline specification.
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What you are actually comparing
NVIDIA GPUs, AMD Instinct accelerators and Google TPUs all execute neural-network math, but they expose very different programming and deployment models.
NVIDIA GPUs: the general-purpose accelerator path
NVIDIA data-center GPUs are programmable parallel processors used for AI, simulation and other HPC workloads. The current Hopper-generation H200 provides 141 GB of HBM3e memory and 4.8 TB/s of memory bandwidth. NVIDIA’s HGX reference documentation lists 180 GB of HBM3e per B200 GPU in eight-GPU HGX systems.
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The practical advantage is the surrounding software ecosystem: CUDA libraries, TensorRT, Triton, vendor-optimized kernels and NVIDIA AI Enterprise form a mature path from model development to production serving. That does not guarantee that every framework release or custom operator works automatically; compatibility still depends on the framework, CUDA version, driver and chosen kernel implementations. It does mean that software already written for CUDA generally has the lowest porting risk.
AMD Instinct: GPU compute with ROCm
AMD Instinct accelerators target AI and HPC. The MI300 family emphasizes high memory density and bandwidth, while ROCm supplies drivers, development tools, APIs, compilers, libraries and runtimes for GPU compute.
AMD does not publish one directly comparable single-card figure for MI300 in the material used here, so a numerical ranking against H200, B200 or TPU products would be misleading. The meaningful AMD question is whether the exact MI300 configuration and ROCm release support your framework, operators, communication libraries and observability requirements.
Google TPU: a compiled ASIC service
Google describes TPUs as custom-developed, application-specific integrated circuits designed to accelerate machine learning and artificial intelligence workloads. XLA compiles a computation graph to TPU TensorCores. Google Cloud currently lists TPU v5e, v5p, v6e (Trillium) and TPU7x (Ironwood).
TPUs can be excellent for dense, regular tensor programs. They are less natural for workloads with frequent branching, CPU-executed custom operators or heavy FP64 requirements. TPU use also ties deployment to Google Cloud capacity, networking and the JAX or PyTorch/XLA programming path.
Published specifications that are genuinely comparable
These figures come from current vendor documentation and use the units shown by each vendor. BF16 throughput is not interchangeable with FP8, FP16 or FP64 throughput, and a chip specification is not a prediction of application performance.
| Accelerator | Published compute figure | High-bandwidth memory | Memory bandwidth | What the figure means |
|---|---|---|---|---|
| NVIDIA H200 | Not stated in the cited product passage | 141 GB HBM3e | 4.8 TB/s | Data-center GPU; actual throughput depends on precision, kernels and software. |
| NVIDIA B200 | Not stated in the cited HGX component passage | 180 GB HBM3e per GPU | Not stated in the cited passage | HGX documentation describes an eight-GPU system. |
| AMD Instinct MI300 | Not stated as one directly comparable single-card value | Official material emphasizes high density | Official material emphasizes high bandwidth | Validate the specific MI300 model, firmware and ROCm release. |
| Google TPU v5e | 197 BF16 TFLOPs | 16 GB HBM | 800 GiB/s | Google Cloud published chip-level specification. |
| Google TPU v6e (Trillium) | 918 BF16 TFLOPs | 32 GiB HBM | 1,638 GB/s | Google Cloud current TPU table value. |
| Google TPU7x (Ironwood) | 2,307 BF16 TFLOPs | 192 GiB HBM | 7,380 GB/s | Google Cloud current TPU table value. |
Notice the unit difference: TPU v5e is listed with GiB/s and GiB, while other entries use GB or TB/s. Do not treat those labels as identical in a capacity model. Also, TPU values are per chip; GPU servers add host CPUs, system memory, interconnect hardware and storage.
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Why memory and interconnect can decide the result
Large language models often fail to fit, or spend too much time moving data, long before the arithmetic units are saturated. Model weights, optimizer states, activations and temporary buffers all consume memory. A device with more usable HBM can avoid sharding or reduce the number of devices required, while higher bandwidth can improve workloads that repeatedly stream large tensors.
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Distributed training adds a second constraint: devices must exchange gradients and activations. The topology of an eight-GPU HGX system, a multi-host GPU cluster or a TPU slice affects collective communication. Compare the complete topology and software collectives, not just the memory on one accelerator.
- Check fit: estimate peak memory for your model, optimizer, sequence length, batch size and checkpoint format.
- Check traffic: measure all-reduce, all-gather and parameter-transfer time at the intended scale.
- Check usable capacity: reserve memory for runtime overhead, compilation artifacts and serving buffers.
- Check scaling: benchmark one device, one host and the final multi-host shape; scaling efficiency can change at each step.
Software ecosystems and porting risk
CUDA and the NVIDIA path
CUDA is the safest starting point for code that already uses NVIDIA-specific libraries, TensorRT, Triton kernels or third-party packages distributed primarily for NVIDIA GPUs. It is also the most forgiving choice when a project combines several frameworks, custom C++ or GPU operators, and changing model architectures.
“Compatible with CUDA” is not a complete acceptance test. Pin the driver, CUDA toolkit, framework build and container image together, then exercise every custom operator and collective at the target precision. A framework may support an H200 or B200 while a particular extension still requires a newer version or a different kernel.
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ROCm offers an open alternative stack covering the driver, compiler, runtime, libraries and development tools. It is attractive when you want a second hardware source, prefer an open toolchain or need the memory characteristics of an Instinct system.
Porting effort is workload-specific. Test framework version support, kernel coverage, collective communication and production observability on the exact MI300 configuration. A model that runs through a high-level framework may still contain an unsupported fused operation, a custom extension or a performance-sensitive collective that needs engineering work.
XLA and the TPU path
TPU programs are compiled through XLA. JAX is designed around this style, and PyTorch/XLA provides a route for PyTorch users. Compilation can produce excellent dense-matrix performance, but it changes the development loop: graph shape, control flow, host callbacks and unsupported operations affect whether the program compiles and how often it recompiles.
Google specifically warns that frequent branching, CPU-executed custom operators and FP64-heavy scientific workloads can be poor TPU fits. Plan for fallback paths only when their latency and data-transfer cost are acceptable; a nominally supported model can still lose its advantage if most of the work leaves the TPU.
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LLM pretraining
For a large pretraining run, first determine the model’s memory and communication shape. NVIDIA is usually the lowest-risk option when the training code, kernels and cluster tooling are CUDA-oriented. H200 and B200 memory capacity can reduce the amount of sharding required, but the final result depends on the complete server and interconnect.
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AMD can be compelling when MI300 memory density, supply diversification or ROCm openness outweighs migration work. Run a representative multi-node test rather than relying on single-device throughput. Verify that collectives maintain efficiency at the intended scale.
TPU v6e or TPU7x can suit a JAX or PyTorch/XLA training stack dominated by regular tensor operations. Include compilation time, recompilation behavior, slice availability and Google Cloud placement in the schedule. A model with dynamic control flow or substantial CPU-side logic may require redesign before TPU training is efficient.
Inference and serving
Serving favors predictable latency, high utilization, memory headroom and an operationally mature runtime. NVIDIA has a strong path when your service already uses TensorRT, Triton or CUDA-specific optimizations. It also offers broad deployment flexibility across on-premises systems and multiple cloud environments.
AMD can lower concentration risk and may offer an attractive memory configuration, but validate the complete serving graph, including preprocessing, postprocessing, batching, quantization path and monitoring. ROCm support for the exact framework and model version matters more than a generic statement that the model “supports AMD.”
TPUs are a good fit when requests can be batched into a stable compiled graph and the service can remain on Google Cloud. Account for compilation and serving orchestration, not just chip execution time. Irregular request shapes or custom CPU operations can reduce utilization.
Fine-tuning and evaluation
Short experiments often reward low setup friction. A CUDA-based codebase with many community extensions usually reaches a working result fastest on NVIDIA. AMD is reasonable when your team already maintains ROCm environments or can constrain the experiment to well-supported operators.
TPUs make sense when the fine-tuning loop is already expressed in JAX or PyTorch/XLA and shapes remain stable. If researchers constantly introduce new Python control flow or custom extensions, the compile-and-debug cycle can dominate the experiment.
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Instinct and NVIDIA GPUs both serve mixed AI/HPC environments, so compare the numerical libraries, communication stack and precision behavior required by the application. TPUs are specialized for machine learning and can be a poor fit for FP64-heavy scientific workloads or algorithms with irregular branching. Do not infer suitability from BF16 peak numbers when the application’s acceptance criteria are FP64 accuracy or legacy CPU/GPU libraries.
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Cloud TPU prices versus GPU economics
Google Cloud’s published US on-demand prices, checked on October 20, 2026, are chip-hour prices:
| Google Cloud TPU | US on-demand price per chip-hour | Qualification |
|---|---|---|
| TPU v5e | $1.20 | Published on-demand rate; region and commitment can change the price. |
| TPU v5p | $4.20 | Published on-demand rate; region and commitment can change the price. |
| TPU v6e (Trillium) | $2.70 | Published on-demand rate; region and commitment can change the price. |
| TPU7x (Ironwood) | $12.00 | Published on-demand rate; region and commitment can change the price. |
These numbers cannot be compared directly with a whole GPU server or virtual machine. A fair cost model includes the host VM, accelerator count, storage, networking, checkpoint traffic, orchestration, idle time, reservations or commitments, and engineering time. NVIDIA and AMD enterprise accelerator prices are generally configuration- and channel-specific; there is no universal US street price on the official pages considered here.
Normalize cost to useful work
- Define the unit: choose completed training steps, tokens processed, examples evaluated or generated tokens.
- Fix the workload: hold model revision, precision, sequence length, batch size, data set and convergence target constant.
- Measure end-to-end time: include input pipeline, compilation, synchronization, checkpointing and recovery overhead.
- Multiply by all-in hourly cost: include host, storage and network charges rather than the accelerator line alone.
- Account for utilization: divide by productive accelerator time, including queue delays and periods when the device is waiting on a CPU or network.
- Repeat at production scale: single-chip results often fail to predict multi-host cost per useful step.
The resulting metric—cost per converged training step or cost per generated token—is more informative than a claim that one platform is simply “cheaper.”
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Decision matrix
| Primary constraint | Best starting point | Why | What to verify |
|---|---|---|---|
| Existing CUDA code, many custom operators | NVIDIA GPU | Lowest expected porting risk and broadest third-party support. | Exact driver, CUDA, framework and kernel versions. |
| Open stack or second supply path | AMD Instinct | ROCm provides an alternative software and hardware path with high-memory Instinct systems. | MI300 operator coverage, collectives, observability and multi-node scaling. |
| JAX or PyTorch/XLA, dense static graphs | Google TPU | XLA can compile regular tensor programs efficiently. | Compile stability, shape changes, host fallbacks and Cloud TPU capacity. |
| FP64-heavy or irregular scientific code | NVIDIA or AMD GPU, subject to library tests | TPU architecture is not aimed at this workload profile. | Numerical accuracy, FP64 throughput and existing scientific libraries. |
| Need to deploy across multiple clouds or on premises | NVIDIA GPU | GPU deployment options are broader than a Cloud TPU-only design. | Actual regional inventory and orchestration support. |
| Lowest apparent hourly accelerator price | Not determinable from list prices alone | Chip-hour rates omit host, utilization and engineering costs. | End-to-end cost per useful result. |
A practical evaluation procedure
Run this process before committing a production workload to a different accelerator family.
- Inventory dependencies. Record framework and compiler versions, CUDA or ROCm libraries, XLA configuration, custom kernels, data-loader behavior and monitoring agents.
- Classify the computation. Mark dense tensor operations, dynamic control flow, CPU callbacks, communication-heavy phases and any FP64 requirement.
- Build a minimal representative slice. Use the real model blocks, precision, sequence length and data pipeline. A toy matrix multiplication is not sufficient.
- Port one complete iteration. Include forward pass, backward pass, optimizer, checkpoint and evaluation code. For inference, include preprocessing, batching and postprocessing.
- Resolve unsupported paths. Replace or rewrite missing kernels, then measure whether a fallback executes on the CPU or triggers expensive synchronization.
- Scale the test. Measure one accelerator, one host and the intended distributed topology. Capture communication time and scaling efficiency.
- Measure steady state and startup. Record compilation, warm-up, memory allocation, checkpoint recovery and steady-state throughput separately.
- Run failure tests. Stop a worker, exhaust memory, vary request shapes and restart the service. Recovery behavior is part of production cost.
- Compare normalized economics. Convert measurements to cost per useful training step or generated token using the all-in price.
- Document the lock-in. List code, data location, orchestration and operational dependencies that would make a later migration difficult.
Common pitfalls and how to avoid them
Comparing peak numbers across unlike precisions
TPU figures in the published table are BF16 TFLOPs. A BF16 number cannot be used to rank an H200, B200 or MI300 for an FP8, FP16 or FP64 application. Report the precision used by the real model and include accuracy checks.
Assuming framework support means complete support
“Runs on PyTorch” or “supports ROCm” may cover the main operators while an extension, fused kernel or collective remains unsupported. Freeze versions and execute the entire graph, not just a sample layer.
Ignoring host and network bottlenecks
Input decoding, tokenization, data loading, checkpoint uploads and collective communication can leave an accelerator idle. Profile the full pipeline and include those resources in cost calculations.
Underestimating TPU compilation behavior
Frequent shape changes, branching or CPU custom operators can cause compile failures, recompilations or fallback execution. Stabilize shapes where possible and measure compile overhead separately from steady-state speed.
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Assuming a vendor benchmark is a universal ranking
Published benchmarks usually select a particular model, precision, batch size, software version and cluster topology. No single neutral benchmark establishes a universal ranking across training, inference, fine-tuning and HPC. Reproduce your target workload under documented conditions.
Planning capacity after the software is finished
Cloud TPU availability is regional and capacity-dependent, while GPU procurement depends on system configuration and channel. Confirm the required slice or server shape before building a schedule around a nominal hourly rate.
Recommendations by team profile
CUDA-first product team
Select NVIDIA unless a measured AMD or TPU pilot demonstrates a material advantage. The value is not only raw speed; it is the ability to use existing kernels, deployment tools and staff knowledge with fewer surprises.
Platform team seeking diversification
Pilot AMD Instinct on a complete production-like path. Start with a workload whose operators and communication patterns are well understood, then expand only after monitoring, upgrades and recovery are proven on ROCm.
JAX research or Google Cloud-native team
Evaluate TPU v6e or TPU7x against the exact compiled graph. Keep a GPU fallback for experiments that introduce unsupported control flow or custom operations, and budget for Cloud TPU capacity planning.
Mixed-framework enterprise
Use NVIDIA as the baseline, then evaluate AMD or TPU per workload rather than forcing one platform across every team. A heterogeneous fleet can be rational when the software boundaries, scheduling and observability are explicit.
Bottom line
NVIDIA is the safest default for heterogeneous AI software and CUDA-based production. AMD Instinct is a credible alternative when ROCm, memory characteristics or supply diversification justify a validation project. Google TPU can deliver strong economics and throughput for stable, dense tensor programs compiled with XLA, but it brings Google Cloud dependence and stricter workload-shape requirements. Choose only after measuring the target model’s end-to-end cost and useful throughput at the scale you will actually run.
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