Xbox 360 RGH, or Reset Glitch Hack, does not alter a game disc or simply replace the dashboard. It injects a precisely timed fault into the console’s staged secure-boot process. A modchip or SMC-assisted circuit slows the CPU, uses the console’s POST codes to identify a boot phase, and sends a reset pulse while a bootloader is comparing hashes. The pulse starts a reset but is too short to complete it; execution continues with the comparison incorrectly reporting equality, allowing modified boot code to run.
Once that authenticated-boot barrier is bypassed, the console can load an attacker-controlled bootloader, hypervisor, kernel and dashboard. The exact circuit, wiring and timing depend on the motherboard revision, which is why Falcon, Jasper, Trinity, Corona and later boards require different methods or timing files.
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What an Xbox 360 RGH mod actually attacks
The Xbox 360 starts through a chain of signed boot stages. Each stage decrypts, hashes or authenticates the next one before handing over execution. RGH targets one of those integrity decisions, rather than the optical drive, a game executable or the dashboard itself.
The first bootloader, 1BL, is built into the CPU. It decrypts the next stage, computes a RotSumSha1 hash, verifies an RSA signature and jumps to the result. On Slim consoles, CB_A decrypts CB_B and checks CB_B’s known hash. If the normal checks succeed, the machine eventually reaches the hypervisor, kernel and dashboard. RGH tries to make one comparison appear valid when the loaded code is actually modified.
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Retail boot sequences by motherboard family
| Family | Documented sequence | Important authentication detail |
|---|---|---|
| Older Phat | 1BL → CB → CD → CF → CD → HV → Kernel → Dashboard |
1BL authenticates the initial CB stage before later loaders run. |
| Newer Phat | 1BL → CB_A → CB_B → CD → CF → CD → HV → Kernel → Dashboard |
CB_A decrypts CB_B and checks its known hash. |
| Slim | 1BL → CB_A → CB_B → CD → CF → CD → HV → Kernel → Dashboard |
The CB_A-to-CB_B check is one of the critical stages for glitch timing. |
The labels identify boot stages, not separate user-facing applications. “HV” is the hypervisor, and “CD,” “CF” and the CB variants are signed loaders that prepare the next stage.
How the glitch works, step by step
- Slow the processor. Native Xbox 360 execution is too fast for a practical fault-injection circuit to hit reliably. RGH1, RGH1.2 and RGH3 can use a CPU PLL bypass on supported chips. The ConsoleMods technical guide describes approximately 128× slowdown on Waternoose and Loki CPUs. RGH2, S-RGH, Mufas and part of RGH3 instead alter the I2C clock-generator path through the HANA chip or South Bridge. The slowdown stretches a normally tiny timing window.
- Observe boot progress. The console exposes an 8-bit POST bus. The glitch logic watches transitions on that bus instead of guessing from a fixed delay after power-on. Free60’s POST documentation describes using post codes “to track the progress of initialization and know when to assert the reset signal.” This makes a timing file specific to a boot phase rather than merely to elapsed time.
- Wait for the authentication comparison. The circuit is programmed for the POST sequence and board characteristics. In one documented Falcon/Jasper timing-file example, it waits roughly 400 ms after POST
0xD9, then waits about 7.2–7.3 ms after POST0xDA. At a 48 MHz reference, the 7.2–7.3 ms interval is approximately 349,821 cycles for timing file 21. - Send a very short reset pulse. The pulse is applied while hashes are being compared. A USENIX analysis of the attack explains that reset begins but does not finish; the CPU keeps executing, while the comparison result is read as zero, or equal, even though the 4BL has been modified. In other words, the pulse does not erase the check. It corrupts the conditions under which the check completes.
- Return to normal execution. After the fault window, the circuit de-asserts the CPU PLL bypass or otherwise restores the normal clock path. The CPU then continues into the modified loader, which can arrange for an attacker-controlled hypervisor, kernel and dashboard.
The essential combination is therefore a slowed CPU, a repeatable phase marker and a pulse short enough to start reset without allowing a clean reset to finish. Removing any one of those elements makes the exploit much less predictable.
Why the reset pulse can bypass a hash check
A secure bootloader normally follows a simple rule: calculate the expected hash, compare it with the loaded image and stop if the values differ. Fault injection aims at the processor’s handling of that decision, not at finding a mathematically matching hash.
During the critical comparison, the reset line is asserted for a carefully selected interval. The processor begins reset-related activity, but the pulse ends before the reset sequence fully takes control. The partially interrupted state can leave the comparison path indicating zero difference. Because execution resumes instead of restarting cleanly, the bootloader proceeds as if the modified image passed authentication.
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This is why RGH is described in technical literature as a fault-injection attack. Harrison and colleagues’ Modern Game Console Exploitation paper summarizes the technique as FPGA modchips injecting faults that skipped buffer-comparison failures in the 360’s 2BL. The attack does not defeat RSA by deriving a private key; it interferes with a particular runtime check.
RGH methods and what changes between them
The names RGH1, RGH1.2, RGH2, S-RGH, Mufas and RGH3 identify families of electrical and firmware techniques. They are not interchangeable presets. Compatibility depends on the board, dashboard-era bootloader and available POST or clock-control connections.
| Method | Typical compatibility described by the guides | Slowdown or control path | Separate glitch chip? | Installation and timing implications |
|---|---|---|---|---|
| RGH1 | Older Phat dashboards and supported early boards | CPU PLL bypass | Generally yes | Uses the original style of PLL timing and requires a compatible dashboard and board layout. |
| RGH1.2 | Common Falcon and Jasper work | PLL slowdown with newer glitch images | Yes | Timing files are tuned to the specific Falcon or Jasper behavior; a value that works on one board is not universal. |
| RGH2 | Phat revisions that use the later approach | I2C clock-generator changes through HANA or the South Bridge | Generally yes | Clock routing and POST availability make wiring and timing different from RGH1. |
| S-RGH and Mufas | Boards covered by those later I2C-based variants | I2C-controlled clock changes | Usually an external controller is used | Requires the matching image, wiring points and board-specific timing data. |
| RGH3 | Supported Phat and Slim revisions | Combination of PLL and I2C techniques with SMC assistance | Can operate without a separate glitch chip | Some boards need additional POST access or an adapter; the exact implementation remains revision-specific. |
The table describes method families, not a guarantee that every board in a named family is compatible. The motherboard identification, NAND contents and dashboard history must be checked before choosing a method.
Why Falcon, Jasper, Trinity and Corona need different timing files
Different clock and signal paths
Each motherboard generation changed CPU behavior, clock-generation hardware and the route used to control or observe the boot process. A timing file encodes delays, pulse characteristics and POST events for that electrical environment. A file selected for a Falcon cannot be assumed to produce the same phase relationship on a Jasper, Trinity or Corona.
POST visibility changed over time
Later revisions removed or altered POST traces, integrated HANA functions into the South Bridge and disabled or filtered signals that earlier glitch circuits relied on. The console may still be booting through the same conceptual stages, but the modchip can no longer observe identical external markers.
Anti-glitch changes added uncertainty
Microsoft’s later revisions introduced measures reported in the technical literature as random delays, redundant checks, reset filtering and disabled POST signals. These changes narrow the useful fault window or make it harder to predict. The final Winchester-era revision is widely regarded as resistant to the established RGH attack; it should not be treated as an ordinary RGH target.
Corona-derived boards may need a postfix connection
On Waitsburg and Stingray boards derived from Corona designs, the CPU POST trace is absent. A postfix adapter may be needed to regain a usable POST connection. That adapter is not a universal performance upgrade: it addresses a missing signal on particular layouts and must match the motherboard and installation diagram.
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A failed first attempt does not disprove the exploit. The CPU can remain unstable immediately after the pulse, and ConsoleMods documents failure categories for pulses that arrive too early, too late or crash the bootloader. The successful window may be only a narrow range of delay and pulse conditions.
- Early pulse: the target comparison has not started, so the reset affects the wrong stage.
- Late pulse: the comparison has already completed or the bootloader has moved on.
- Unstable post-pulse state: the comparison is bypassed, but the CPU does not immediately execute cleanly.
- Wrong timing family: the image or timing file does not match the board’s clock path, POST sequence or CPU behavior.
- Missing POST access: the circuit cannot see the transition it needs, which is a known issue on some Corona-derived layouts without a postfix solution.
There is no authoritative comparative success-rate percentage in the cited technical documentation. Reliability is described qualitatively as dependent on motherboard revision, wiring, timing data and the individual console. Repeated attempts should therefore be diagnosed as timing or signal problems, not “fixed” by assuming one universal delay.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Hardware, NAND access and installation risk
An RGH installation normally involves both software preparation and board-level electrical work. ConsoleMods lists a NAND programmer, soldering iron, flux and 28 or 30 AWG wire among the minimum requirements. The NAND programmer is used to read and write the console’s flash storage and to verify that the intended boot files are present. The soldered wires carry clock, reset, POST or SMC-related signals according to the chosen method.
Do you need a glitch chip?
Often, yes. RGH1, RGH1.2 and RGH2 installations conventionally use a controller that monitors POST, generates the delay and produces the pulse. RGH3 can use the console’s SMC together with PLL and I2C wiring, so a separate glitch board may not be required on supported revisions. “Chipless” does not mean solder-free; it still requires board-level connections and compatible software.
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Do you need a NAND programmer?
For a conventional installation, yes. NAND access is needed to back up the original flash, install or prepare modified boot data and recover from mistakes. Keeping an untouched dump is a basic safeguard because a wiring error or bad image can leave the console unable to boot.
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When is a postfix adapter required?
A postfix adapter is relevant when the motherboard does not expose the POST connection needed by the selected timing method, particularly on some Waitsburg and Stingray boards derived from Corona. It does not replace the need to identify the board or choose a compatible RGH method.
Why soldering quality matters
These signals are timing-sensitive. Excess solder, lifted pads, shorts, long or poorly routed wires and inadequate flux cleaning can change signal integrity or permanently damage a trace. ConsoleMods warns that inexperienced soldering can brick a console. The practical risk is not limited to a failed glitch: a damaged NAND connection, power rail or pad can make recovery substantially harder.
A safe way to interpret an installation diagram
- Identify the exact motherboard. Do not choose a method from the console’s case name alone. Confirm the board revision and whether it is a Phat, Trinity, Corona-derived, Waitsburg, Stingray or Winchester-era design.
- Record the dashboard and NAND state. Save a verified original NAND dump before writing anything, and confirm that multiple reads match.
- Match the method to the board. Select RGH1, RGH1.2, RGH2 or RGH3 only when the documented compatibility includes that revision and dashboard generation.
- Confirm signal availability. Check whether POST, PLL, I2C, reset and SMC points are present. If CPU POST is absent, determine whether the board-specific solution calls for a postfix adapter.
- Use the corresponding timing file. Treat the timing file as engineering data for that board and CPU, not as a generic speed setting. Do not substitute a Falcon/Jasper value on a different revision.
- Verify every connection before power-up. Inspect for shorts, lifted pads, incorrect wire destinations and unclean flux residue. A continuity check and a second visual inspection are cheaper than NAND or motherboard repair.
- Diagnose boot behavior from evidence. Record POST behavior, pulse attempts and failure patterns. Repeated early, late or crash-type failures point toward timing, signal access or wiring rather than a need to keep changing unrelated software.
What RGH does—and does not—change
RGH does not make the console’s cryptographic signatures mathematically valid. It changes whether a particular bootloader check can stop execution. After that check is bypassed, modified software can control later stages, which is why the effect reaches the hypervisor, kernel and dashboard.
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Quick Recap
Key points to remember
- RGH is a fault-injection attack against a staged secure-boot integrity check.
- CPU slowdown creates a usable timing window; the documented Waternoose/Loki example is approximately 128×.
- POST codes provide a repeatable reference for locating the boot phase.
- The reset pulse is deliberately too short to complete a reset, allowing execution to continue with a faulted comparison result.
- Motherboard revisions changed clock control, POST visibility and anti-glitch behavior, so hardware and timing files are revision-specific.
- NAND access and fine soldering are part of the job, and a wiring or flash error can brick the console.
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