The Tool Desk
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What FPGA simulation can—and cannot—tell you
Simulation lets you drive a design’s inputs and observe its outputs over time without programming a physical FPGA. Start with RTL or behavioral simulation to check whether the described logic responds as expected in the scenarios you test. AMD describes simulation at behavioral, post-synthesis, and post-implementation stages; later stages can model functional or timing behavior depending on the flow and setup (AMD Vivado Verification).
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A simulation only establishes what happened in the modeled design under the inputs and conditions you supplied. It does not show that untested cases work, that the implementation meets its timing requirements, or that board-level wiring, pins, clocks, external devices, and electrical conditions are correct. AMD’s guidance is that early simulation helps find issues earlier in the design cycle; it should be treated as one verification step, not a guarantee of hardware success.
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Build a testbench around the design’s requirements
Identify the design under test
Choose the module or entity to test, then write down its inputs, outputs, reset behavior, clock domains, and expected responses to important input sequences. Derive expected results from the design specification or requirements—not merely from assumptions repeated in the RTL. Where practical, use independent checks so the testbench is less likely to reproduce the same mistaken assumption.
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Drive inputs and check outputs
A testbench is separate from the design under test (DUT). It instantiates the DUT, supplies clocks, reset and input stimulus, and observes the outputs. Intel describes this stimulus-and-capture role in its third-party simulation guide. Initialize inputs at time zero and make the conditions repeatable; AMD recommends this approach in its UG900 Logic Simulation guide.
Use explicit checks for important expected values and properties. Waveforms help you inspect sequence and timing, but a plausible-looking waveform is not a pass/fail test by itself. A useful testbench should make failures visible, for example by reporting a mismatch or ending with a failure status when a required condition is violated.
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Cover ordinary, boundary and failure cases
Choose cases from the specification rather than relying on a single demonstration sequence. Depending on the design, check reset and initialization, normal transactions, boundary values, protocol ordering, and relevant error conditions. For clocked logic, make stimulus and checks relative to the intended clock edges, and account for any distinct clock domains rather than treating the design as if it had one universal clock.
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- Select a compatible simulator. Confirm that it supports the HDL and language features used, any mixed-language design, the target FPGA’s simulation models, and the generated IP or encrypted models your project needs. AMD’s Vivado Simulator is an event-driven HDL simulator supporting behavioral and timing simulation, including single- and mixed-language designs (AMD Vivado Verification). Other simulators may also fit, but support depends on the exact language, IP, libraries, edition and tool release.
- Set up the project files and libraries. Include the DUT sources, testbench sources, simulation libraries, and any required generated IP models. Use the setup intended for the target device and the release used to generate or compile the project.
- Set the testbench as the simulation top. The simulator should elaborate the testbench, which instantiates the DUT, rather than treating the DUT alone as the simulation top when the testbench is intended to provide stimulus.
- Compile, elaborate and run. Resolve compilation errors first, then elaborate the selected testbench and run the simulation. Intel’s Quartus generic workflow explicitly calls for identifying design, library and testbench files; selecting the top-level testbench; assigning logical libraries and compilation options; determining elaboration options; and scripting compile, elaborate and simulate (Intel FPGA Simulation Generic Workflow, v25.1).
- Inspect results and repeat. Check automated pass/fail results and examine waveforms when useful. Fix the RTL or testbench as appropriate, then rerun the same tests so changes are checked against a repeatable baseline.
Exact menus, library setup and IP-model steps vary by vendor, simulator, device and release. If elaboration or simulation fails on a vendor primitive or IP block, verify that the correct model and library are present and that their versions match the project; a successful compile of the user RTL alone does not establish that all dependencies are modeled.
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Account for tool-specific startup and reset behavior
Do not assume simulator startup is identical across tools or stages. AMD’s UG900 v2023.1 documents a default global set/reset (GSR) pulse that holds registers in reset for the first 100 ns in applicable post-synthesis and post-implementation timing simulations. The guide recommends initializing inputs at time zero and starting the clock before GSR is released. This is a Vivado flow consideration for the documented version and simulation stages, not a universal HDL reset rule. Check the documentation for the exact simulator and flow you use.
Move beyond behavioral simulation when risk warrants it
Post-synthesis and post-implementation simulation
RTL simulation checks the modeled behavior before implementation. Post-synthesis or post-implementation simulation can check a later representation of the design, including timing behavior when the flow and models support it. AMD documents these stages in its verification overview. Intel likewise describes simulation and formal verification across design stages in its third-party simulation guide.
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These checks can be useful for higher-risk designs or flows where implementation changes, vendor primitives, or timing behavior merit additional verification. They are not a replacement for reviewing constraints and implementation timing reports.
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Timing simulation is not static timing analysis
Timing simulation models delays in a simulated design and tests selected input sequences. Static timing analysis evaluates implementation paths against timing constraints; it is the essential way to determine whether the implemented design meets its timing requirements. Neither a functional RTL pass nor a plausible timing waveform alone establishes timing closure.
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Constrain and inspect timing for the target system
Timing constraints describe the environment the FPGA must work in, including clock requirements and the timing relationship of external inputs and outputs. For Intel Quartus, input-delay constraints express timing assumptions for signals arriving from outside the FPGA. Intel notes that the Timing Analyzer’s check_timing can identify issues such as non-clock input ports without input-delay constraints (Intel Input Constraints, Quartus Prime Pro Edition Timing Analyzer v25.1).
Use realistic constraints for the intended system, then inspect the relevant timing analysis reports after implementation. Missing or unrealistic constraints can make a timing result misleading: the tool can only evaluate the assumptions it has been given. Check that the clocks and relevant input and output ports are covered, and resolve reported constraint problems before treating timing as verified.
Use simulation as a gate before board programming
Before programming hardware, confirm that the intended testbench runs reproducibly, required checks pass, and important scenarios from the specification have been exercised. Then review the implementation timing results and verify the board-specific assumptions that simulation cannot establish, including pin assignments, external connections, clock source and interface behavior. Programming and testing the board remains necessary to check integration with real hardware.
For a small, low-risk design, a well-constructed RTL testbench and a timing review may be an appropriate verification depth; complex interfaces, vendor IP or high-consequence behavior can justify additional formal, post-synthesis or post-implementation checks. Choose the depth based on project risk and the capabilities of the exact tool flow, rather than assuming one simulator or stage is universally sufficient.
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