Start with a board whose FPGA family has a documented open-source toolchain, then follow the full path from HDL to a programmed device. For a concrete first project, YosysHQ’s nextpnr documentation shows a small Verilog “blinky” design for the iCEstick: Yosys synthesizes it, nextpnr places and routes it, and IceStorm tools create and upload the bitstream.
Choose the FPGA before choosing the tools
Open-source FPGA development is not one universal toolchain that works with every chip. Synthesis, place-and-route, device databases, bitstream generation, and programming depend on the FPGA architecture. Start by identifying the exact family and part on a board, then check that the relevant projects support it and that you can obtain the board’s pin constraints and programming instructions.
The documented iCEstick example is a straightforward learning path for an iCE40 device. The iCEBreaker FPGA project describes its board as an educational platform for learning an open-source FPGA flow, making it another iCE40-oriented option to investigate. These examples do not establish that every board revision or FPGA is supported; verify the exact device and board documentation before purchasing or following a tutorial.
Understand what each tool does
- Yosys synthesizes an HDL design into a representation for implementation. The iCE40 example uses Yosys’s
synth_ice40flow and produces a JSON file. - nextpnr performs place and route: it maps the synthesized design onto the FPGA and determines connections between its resources. Its documentation has distinct setup paths for iCE40, ECP5, and Nexus architectures.
- Architecture-specific projects and tools supply device information and support the bitstream and programming stages. The nextpnr FAQ distinguishes Project IceStorm for iCE40, Project Trellis for ECP5, and Project X-Ray for Xilinx 7-series.
For broader context on the Yosys and nextpnr framework, see the Yosys+nextpnr framework paper.
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- Designed for students and beginners looking to understand Digital Logic, fundamentals of FPGAs
- Features the Xilinx Artix 7 FPGA compatible with Vivado Design Suite WebPACK Edition (free download available from Xilinx)
- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
- Expansion opportunities with four Pmod ports including 3 standard 12-pin Pmod ports and 1 dual
- Does NOT ship with micro USB cable
Run the documented iCEstick blinky flow
The example’s sequence is HDL source, synthesis, place and route, bitstream conversion, and programming. The commands below are documented by nextpnr for the iCEstick example; they are not a guarantee that the tools are installed or that the commands have been independently tested on your computer.
- Prepare the source and constraints. Use the example’s Verilog source file,
blinky.v, and its board-specific pin-constraint file,blinky.pcf. The constraints assign design signals to the board’s physical pins. - Synthesize with Yosys. This command targets the top-level module named
blinkyand writes the synthesized design to JSON:yosys -p 'synth_ice40 -top blinky -json blinky.json' blinky.v - Place and route with nextpnr. The example selects the
hx1ktarget, reads the JSON and PCF files, and writes an ASCII bitstream file:nextpnr-ice40 --hx1k --json blinky.json --pcf blinky.pcf --asc blinky.ascConfirm that the option naming the FPGA variant matches the actual part on your board. Do not substitute another board’s pin constraints.
- Convert the bitstream. IceStorm’s
icepackconverts the ASCII representation into the binary file used for programming:icepack blinky.asc blinky.bin - Program the board. With the board connected and the appropriate programmer available, use
iceprogto upload the binary bitstream:iceprog blinky.bin
Each stage consumes the output of the previous one. If a command fails, check that the corresponding tool is installed, that you are in the directory containing the named files, and that the target FPGA and pin constraints match the board. The nextpnr README provides setup instructions and lists build prerequisites including CMake, a C++17 compiler, Python, Boost, and Eigen3; requirements vary by architecture and host. Binary-package availability and ease of setup for a particular operating system are not established here, so consult the current project instructions for your system.
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- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
Check board compatibility before buying
Search for an iCEstick FPGA development board if you want to follow the named example, but confirm these details against the current listing and board documentation:
- The FPGA family and exact variant match the tutorial’s target.
- The board revision is documented and its pin assignments match the constraint file.
- A compatible programmer or cable is included, or you know what additional hardware is needed.
- The current project documentation covers the board and the host operating system you plan to use.
Current prices, stock, specific listings, and board-revision compatibility are not established by the cited project pages. Treat the iCEstick as a documented example, not a blanket recommendation for every iCE40 board.
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- [USB2.0 HS interface] The 27MHz crystal generates the clock for HDMI display, onboard MS5351 clock generating chip also provides mutiple clocks.Support Serial communication, high-speed SPI reception.
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How to choose a different open-source FPGA board
If you are considering a family other than iCE40, verify the whole workflow rather than relying on a claim that a chip is “open-source friendly.” Use the project documentation for that architecture to check:
- Whether synthesis supports the family and exact device.
- Whether nextpnr and the associated device database support the target.
- How the bitstream is generated and which project provides that support.
- Whether programming tools support the board and its revision.
- Whether the board has usable examples, pin constraints, and beginner documentation.
- What installation steps and hardware connections your operating system and board require.
For example, nextpnr documents separate setup routes for iCE40, ECP5, and Nexus, while the FAQ identifies different architecture projects for bitstream-related support. Do not infer that support for one family carries over to another or that every commercial FPGA is covered.
Quick Recap
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- Digilent Basys 3 Artix-7 FPGA Trainer Board: Recommended for Introductory Users
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