A semiconductor supply chain turns a design into a finished chip through several connected stages: design, wafer fabrication, and assembly, testing, and packaging (ATP). Specialist companies often handle different stages, while equipment, materials, chemicals, software, and intellectual property flow in from a wider supplier network. A chip may pass between multiple firms—or stay within an integrated manufacturer—so no single company or country necessarily controls the whole chain.
What moves through a semiconductor supply chain?
The chain is more than a sequence of factories. It coordinates a chip’s design with a manufacturing process, supplies the tools and materials needed to make it, and converts fabricated structures on a wafer into tested, packaged components that can be installed in electronic products.
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A simplified path is:
- Design: Define the chip’s functions and create a circuit design compatible with a manufacturing process.
- Wafer production and front-end manufacturing: Prepare semiconductor wafers and repeatedly process them to form circuit patterns and structures.
- Assembly, testing, and packaging: Separate the completed wafer into dies, package them so they can connect to a larger system, and test them.
- Downstream integration: Incorporate packaged chips into printed circuit boards and finished electronic products.
Alongside those steps, suppliers provide manufacturing equipment, substrates, electronic gases, wet chemicals, photoresists, packaging materials, design software, and reusable intellectual property. These inputs are essential to production even when their suppliers do not design or manufacture the final chip.
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This is a simplified map rather than a universal itinerary. Companies can combine business roles, outsource selected work, or handle multiple stages internally. The chip type, process, and manufacturer determine the actual route.
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How does chip design prepare a product for manufacturing?
Design translates a product or system need into a circuit design. It is not simply a matter of drawing a circuit in software: designers have to work with the capabilities and requirements of a manufacturing process, and the design must be prepared for the way it will be made.
The OECD identifies three important design inputs used by fabless firms, system firms, and integrated device manufacturers (IDMs): electronic design automation (EDA) tools, IP cores, and process design kits (PDKs).
- EDA tools support the electronic design work.
- IP cores are reusable functional blocks that can be incorporated into a design.
- PDKs help designers work with a particular manufacturing process.
These inputs link the design stage to fabrication. A reusable block or design tool does not remove the need to make the full chip design compatible with the process that will manufacture it. Design services, tools, IP, and manufacturing therefore belong to connected parts of the same chain.
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Which kinds of companies handle each stage?
Terms such as fabless, foundry, OSAT, system firm, and IDM describe business models, not sealed-off categories. One company can perform more than one role, and its role can differ from product to product.
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| Business model | Typical role in the chain |
|---|---|
| Fabless company | Designs chips and outsources manufacturing to foundries; typically sells chips rather than operating its own wafer fab. |
| Foundry | Operates fabrication plants, or fabs, to manufacture semiconductors for other firms on a contract basis. |
| OSAT | An outsourced semiconductor assembly and test provider, typically supplying ATP services to fabless firms, system firms, and IDMs. |
| Integrated device manufacturer (IDM) | Can carry out multiple stages, from design through packaging, but may outsource selected stages or provide contract manufacturing. |
| System firm | Designs chips for its own products or services and typically relies on foundries and OSATs for production. |
A common route might take a design from a fabless company to a foundry for wafer fabrication and then to an OSAT for assembly and testing. But that should be read as an example of a handoff, not a rule for every chip. An IDM may perform several steps itself; other firms may mix internal capacity with contracted work. The OECD notes that companies can combine foundry, IDM, and OSAT activities.
The important question when identifying a company’s place in the chain is what it does for the particular product and stage under discussion. Calling a firm a foundry, for example, does not establish that it also designed the chip or packaged it.
What happens during wafer fabrication?
Front-end manufacturing forms circuit patterns on a semiconductor wafer. Rather than create the whole chip in one operation, fabrication uses repeated processing steps, with specialised equipment and materials supporting different parts of the work.
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- Polishing: Prepare or refine a wafer surface as part of the process sequence.
- Deposition: Add material layers.
- Resist application: Apply a photosensitive resist used in patterning.
- Lithography: Use a patterning process to define features on the wafer.
- Etching: Remove selected material to transfer patterns into a layer.
- Ion implantation: Introduce ions into selected regions of the semiconductor.
- Resist removal: Strip resist after it has served its role in a patterning sequence.
These steps recur as the wafer is processed. The list is illustrative, not a claim that every chip uses an identical sequence or that these are the only operations involved. Equipment categories identified by the OECD include lithography, resist processing, metrology and inspection, etching, deposition, cleaning, and chemical-mechanical planarisation (CMP).
Fabrication also depends on a range of consumables and inputs. The OECD lists silicon or other substrate wafers, electronic gases, wet chemicals, photoresists, and CMP materials among the inputs. Equipment and materials suppliers are therefore part of the manufacturing chain even though they do not necessarily make chips themselves.
Wafer fabrication is the most capital-intensive stage in the chain, according to the OECD’s overview. The scale of equipment spending gives one indication of the industrial infrastructure involved: the OECD’s 2025 overview reports SEMI’s estimate that the global semiconductor manufacturing equipment market was around USD 139 billion in 2024. That figure is for manufacturing equipment, not chip sales or the value of the semiconductor industry as a whole.
How do fabrication, testing, and packaging become a usable chip?
When front-end processing is complete, the wafer contains multiple chip dies. The wafer is cut into individual dies, which then need assembly and packaging before they can connect to a larger system. ATP providers can carry out this back-end work for fabless companies, system firms, and IDMs.
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- Integrated Antenna: Features PCB trace antenna built directly on-board for immediate testing and development without requiring external antenna components
Packaging materials can include lead frames, substrates, bonding wires, and die-attach materials. Packaging is not just an outer covering: it is part of the manufacturing process that prepares the die for connection and use. Testing checks for defects and performance before a packaged component moves downstream toward board and product integration.
Advanced packaging can bring more than one integrated circuit together at the package level. The U.S. Department of Energy (DOE) assessment describes heterogeneous integration, including chiplets or multiple integrated circuits in one package, and vertical stacking using through-silicon vias. These approaches can enable greater transistor density at the package level and a wider mix of functions in one package. They are capabilities, not a guarantee that every advanced package will be more efficient.
Once packaged and tested, chips move to downstream integration, where they are incorporated into printed circuit boards and finished electronic products. This final step is separate from wafer fabrication and ATP: a packaged component is not, by itself, the complete electronic system in which it will operate.
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What does a real company’s production illustrate?
TSMC’s 2024 annual report describes a pure-play foundry model and reports work on advanced packaging and 3D stacking, including CoWoS, InFO, and SoIC. Its reported production figures show the breadth of one company’s operations in that year:
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| TSMC company-reported figure | Scope |
|---|---|
| 12.9 million 12-inch-equivalent wafer shipments | TSMC shipments in 2024. |
| 11,878 products | Products manufactured by TSMC in 2024. |
| 288 process technologies | Process technologies used by TSMC in 2024. |
| 522 customers | Customers served by TSMC in 2024. |
These are company-reported, year-specific figures. They illustrate the scale and variety of one foundry’s activity; they do not measure the entire semiconductor industry or show that other manufacturers have the same product mix or business model.
Why can a supply chain be vulnerable even when it has many suppliers?
Semiconductor supply is multi-tiered and geographically dispersed. Making chips can take months, and production depends on materials, equipment, and components supplied through several layers of companies. A disruption at an upstream supplier can therefore affect manufacturers further along the chain, even if that supplier does not make a finished chip.
Geography also needs careful interpretation. The Semiconductor Industry Association (SIA) reports that 95% of roughly $27 billion in equipment and materials consumed by semiconductor players in the United States is sourced from suppliers headquartered in the United States, Europe, and Japan. This is a statistic about U.S. consumption and suppliers’ headquarters locations. It does not say where those inputs are manufactured, and it is not a measure of global sourcing.
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Specialisation and concentration can create vulnerability as well. The UK National Semiconductor Strategy discusses those structural risks and notes that fabrication needs specialist materials and equipment, while packaged chips need testing before end-use integration. It also cites regional-capacity figures from a 2021 BCG/SIA report. Those figures describe historical capacity for particular chip categories; they should not be treated as current regional shares.
How to read claims about semiconductor dominance
There is no single defensible ranking of which country or company “controls” semiconductors across all stages. A comparison is meaningful only when it identifies what is being compared.
- Stage: Design and IP, wafer fabrication, ATP, or an upstream supplier input are different activities.
- Business model: A fabless chip designer, foundry, OSAT, system firm, and IDM perform different roles, though roles can overlap.
- Technology or chip category: Regional capacity claims need to be tied to the chip type or technology covered.
- Year: Production and capacity figures are time-specific and should not be presented as timeless facts.
- Geographic measure: Supplier headquarters, manufacturing location, consumption, and installed capacity describe different things.
For example, the SIA’s U.S. consumption statistic concerns the headquarters of suppliers for equipment and materials, whereas the 2021 regional-capacity figures cited by the UK strategy concern historical capacity in specified chip categories. Neither figure alone describes control of the full supply chain.
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