Chipmakers adopt a new lithography process when it can reliably make the features a product needs—and when the benefits across the entire manufacturing flow justify the added cost, yield risk, design work and supply-chain preparation. The decision is rarely an all-at-once switch: a company may use a new method on selected layers or products while keeping established techniques elsewhere.
What chipmakers are deciding
Lithography creates patterns on a silicon wafer by transferring a design through a mask and a light-based exposure process. Those patterns help define a chip’s transistors and wiring. A lithography change can enable smaller or more intricate features, greater density, or improved performance and power. It can also change how many exposures and other process steps are needed to make the chip.
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The choice is therefore not simply whether a newer scanner can print a finer line. A chipmaker must determine whether the proposed method works repeatably as part of the integrated process, whether it improves the product enough to matter, and whether the company and its suppliers can support production at the required scale.
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A free scan shows the junk files, broken settings and background clutter dragging Windows down - then fixes them in one click.Free scan · Windows 10 & 11Node names alone do not answer those questions. As ASML explains, node labels are generation names; they are not a sufficient description of a company’s manufacturing choices or of which lithography techniques it uses on each layer. DUV and EUV, for example, can coexist: EUV is used for the most intricate layers while DUV continues to pattern others.
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How do chipmakers decide whether the process is technically ready?
Engineers first compare the process’s patterning capability with the product’s requirements. They examine whether it can print the relevant structures at the needed critical dimensions, with acceptable pattern fidelity and alignment between layers. A promising result on one exposure is not enough: the pattern must remain controllable across the integrated flow.
Prove repeatability and control
The process must demonstrate acceptable defectivity, overlay, critical-dimension stability and process stability, as well as usable throughput and availability. A defect or alignment error can make a die unusable, so a nominal resolution advantage is valuable only if it can be achieved consistently across production wafers.
TSMC’s 2024 annual report describes work on wafer yield for 2nm risk production, EUV scanner application efficiency, material defects, planarization and overlay. Its A14 mask work emphasizes critical-dimension uniformity, pattern fidelity, overlay accuracy and mask-defect inspection. These examples show that qualification concerns extend from the exposure itself to the materials and layers surrounding it.
Account for the technology’s process trade-offs
Higher resolution can bring new integration constraints. Imec notes that High-NA EUV’s larger numerical aperture reduces depth of focus compared with 0.33-NA EUV. Its patterning work therefore evaluates depth of focus alongside resolution, defectivity and critical-dimension stability, and can require process changes such as thinner resist films. A capability that improves one dimension must still fit the process window needed for reliable manufacturing.
These checks answer a practical question: can the technique repeatedly deliver the intended patterns with enough control to make good chips, rather than merely demonstrate a technically impressive image? The answer has to come from process development and qualification, not from a node label or a scanner specification alone.
How do chipmakers balance yield and cost?
The economic comparison is between complete manufacturing flows, not just between the purchase price or capability of two scanners. A new exposure method might reduce the number of patterning steps on a critical layer, but it may also require new equipment, materials, masks, integration work, training and qualification. Companies weigh those costs against usable output, yield risk, cycle time and the product benefits the new process enables.
Count the steps the whole flow needs
Multiple exposures can be used to achieve tighter pitches, but each added exposure can add process cost and complexity. Imec says High-NA EUV may allow some critical layers to move from multi-patterning back to single patterning. That could relieve cost, yield and cycle-time pressure. ASML likewise says fewer production steps can reduce defects, cost and cycle time.
Those are potential benefits, not guarantees that every High-NA layer or product will be cheaper. A fair comparison asks what happens to the entire sequence: exposure and mask count, associated process steps, defect opportunities and the time and resources needed to produce a usable die. New methods also bring their own integration and supply costs. The sources do not establish a universal equipment-price break-even, yield hurdle or financial formula, so there is no single numerical rule that determines adoption.
Relate manufacturing gains to the product
Even a successful process improvement has value only if it helps the products customers need. A performance- or density-focused design may benefit from a capability that is not worth its cost for a more price-sensitive product. Demand matters too: a manufacturer needs a reason to qualify the process and prepare production capacity for the intended product mix.
TSMC’s N7 platform page lists applications in smartphones, high-performance computing, automotive, consumer electronics, networking and other sectors. That range illustrates why the same process choice need not have identical value across markets. A chipmaker evaluates whether the particular product portfolio can use the benefits, rather than assuming that technical novelty alone creates demand.
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Why design migration and customer readiness matter
A process change affects customer designs as well as factory equipment. If design rules, device models, intellectual property and electronic-design-automation tools are compatible, customers may be able to carry forward more of their prior work. If they are not, redesign and re-tape-out work can add time, cost and risk to the transition.
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TSMC’s N6 is a concrete example of design continuity: the company says N6 uses additional EUV layers while retaining N7 design rules, device models, IP and EDA availability. It says N7 customers can sustain their design investments when moving to N6. For re-tape-outs, TSMC attributes yield improvement to fewer masks and a simpler process. This is a specific feature of that transition, not a promise that future node changes will preserve compatibility.
TSMC also states that its N7 platform delivers 30% better speed, 55% lower power and three times the logic density versus N16. Those are TSMC’s stated N7 comparison figures, with N16 as the baseline; they should not be read as a general forecast for a different node migration or as a measure of the lithography technique alone.
What makes a new lithography process ready for production?
A scanner does not make a production-ready process by itself. The manufacturing ecosystem has to support the patterning method: photomasks, resist and underlayer materials, metrology, imaging, optical proximity correction, etch, wafer handling and supplier capability all have roles. Design solutions must also let customers use the new process effectively.
Imec describes shared High-NA preparation across these areas. Its lab work is intended to help foundries and integrated device manufacturers de-risk the technology and develop use cases before scanners are operational in production fabs. That distinction matters: a research or development installation can advance ecosystem readiness without proving that a process is qualified for high-volume manufacturing.
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1Scan for outdated or missing drivers - takes under a minute2Clear out junk files and repair common Windows errors3Fix the driver behind crashes, sound loss and screen glitchesMask infrastructure is another example. In a September 8, 2026 announcement, ASML and TSMC described work on a larger photomask format for High-NA. Their announcement says production will begin with current six-inch masks; a later move to twelve-inch masks is expected to improve productivity, lower costs and remove stitching constraints. Those are announced plans and expected benefits, not evidence that the larger format has already become an industry-wide production standard.
Why does a new process reach production selectively?
Adoption can start with a subset of layers or products because the technical and commercial case differs across a chip. Some layers may need the new method’s resolution; other layers may not. A manufacturer can therefore qualify and deploy the technique where it brings enough value, rather than replacing every established exposure method in one step.
Intel and ASML reported on September 7, 2026, that High-NA EUV was being used in high-volume manufacturing at Intel Foundry on selected layers for a subset of Intel Core Ultra Series 3 processors made on Intel 18A. The companies said overlay, throughput and availability were meeting Intel Foundry’s expectations, and that customers could use the existing six-inch mask format with floor-planning or stitching approaches. This is a company-reported production example; it does not establish universal adoption or describe the schedules of other manufacturers.
The same announcement said more than one million wafers had been processed across certification, testing, research and development, and volume production. That combined figure should not be mistaken for one million production wafers. It indicates activity across several stages, not a production-volume threshold that other technologies must meet.
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Imec’s March 18, 2026 announcement about installing an EXE:5200 High-NA system in its 300mm Leuven cleanroom said qualification was expected by Q4 2026. That statement was an expectation made at the time; it is not itself confirmation that qualification occurred. Development facilities and production fabs serve different roles in the path toward broader deployment.
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A practical framework for comparing two lithography flows
For a proposed change, chipmakers have to compare the incumbent process with the new one across related dimensions. No single metric is enough: a resolution gain can be offset by process instability, poor yield, added steps or insufficient customer demand.
| Decision area | What the chipmaker evaluates | Why it matters |
|---|---|---|
| Patterning capability | Resolution, critical dimensions, pattern fidelity and overlay on the target structures and layers | Determines whether the process can create the features the product requires. |
| Manufacturing performance | Yield, defectivity, stability, throughput, availability and cycle time | Shows whether capability translates into repeatable, usable production. |
| Flow economics | Exposure and mask counts, extra process steps, equipment and material needs, and cost per usable die | Captures both the potential savings from a simpler flow and the investment and risk of adopting it. |
| Design migration | Compatibility of design rules, models, IP and EDA tools, and the redesign or tape-out work required | Changes customer cost, schedule and willingness to move designs. |
| Ecosystem readiness | Availability of masks, resist, metrology, imaging, OPC, etch, handling and qualified suppliers | A scanner must work within a complete manufacturing and design ecosystem. |
| Product and customer fit | Whether the benefits match target products and whether demand justifies qualification and capacity | Connects factory readiness to a commercially useful product portfolio. |
These axes are a decision framework, not a published scoring system. ASML, imec and TSMC describe the relevant technical and flow considerations, but do not specify a universal cutoff for yield, cost or adoption. Companies have to judge the trade-offs for their own technology, customers and products.
What the examples say about adoption timing
The progression from development to broad use depends on several pieces advancing together: patterning performance, process control, integration, design support, suppliers and product demand. A technology can be available for testing before it is ready for a production fab; it can be usable in high-volume manufacturing for selected layers before it is widely used elsewhere. A company’s reported milestone should therefore be read in terms of the products, layers and manufacturing setting it actually covers.
TSMC’s scale helps explain why readiness is not merely a scanner decision. An ASML-TSMC release reported 305 distinct process technologies, 12,682 products and 534 customers in 2025. Those figures describe the breadth of TSMC’s manufacturing and customer environment; they are not targets or thresholds for adopting a new lithography process.
Ultimately, chipmakers adopt when a new method can meet manufacturing requirements and improve outcomes for the products that need it, while the complete flow and supporting ecosystem are ready. Because each company’s process, design base and product mix differ, a selective rollout can be the rational endpoint—not just a temporary step toward using the technique on every layer.
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