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Advanced chipmaking partnerships bring together a chip customer, a foundry, and specialist companies to turn a product idea into a manufacturable chip. The foundry contributes more than wafer fabrication: it also provides process-specific design rules and tools, access to intellectual property (IP), engineering support, and often packaging capabilities. Electronic design automation (EDA) vendors, IP providers, design services, cloud platforms, and assembly-and-test partners help make the design work with that particular process and production flow.
The exact division of work, costs, capacity commitments, and IP rights depend on the project. Public descriptions explain what foundries and their partners say they offer, but they do not disclose the terms of every customer engagement.
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What does a foundry contribute?
A foundry manufactures chips for customers that design or commission them. In advanced partnerships, its role starts well before a design reaches the factory. The foundry develops a manufacturing process and provides the information and technical resources needed to design for it, then fabricates the resulting chips and may also support packaging and test.
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- Process technology and design rules: The foundry defines the manufacturing options and constraints that shape how a chip can be designed.
- Design enablement: Process design kits (PDKs), libraries, reference flows, and process-specific IP help engineers create and check a design for the selected process.
- Manufacturing: The foundry runs wafers and works with the customer toward qualification and production. Manufacturing quality, productivity, and capacity are part of the foundry contribution, though public platform descriptions do not establish a universal production schedule or contract.
- Packaging and related services: Depending on the offering, the foundry may provide advanced packaging, assembly, or test itself, or work with specialist partners that do.
TSMC’s 2025 Annual Report describes advanced and specialty processes, 3DFabric stacking and packaging, manufacturing productivity and quality, and design ecosystem support as parts of its foundry services. TSMC also reported that N2 volume production began in 2025 as planned; that is the company’s status report for that process and year, not a general timetable for new processes.
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- 5 x 5 inches, 0.67 ounces, 0.03 inches thick. Some wafers are marked with alignment marks.
- The pattern is produced by light diffraction, and its reflective appearance changes with the viewing angle.
- Silicon wafers are fragile—please handle with care.
- Circuit details can be examined under a microscope.
How does a partnership take a chip from requirements to production?
The work is a connected design-and-manufacturing effort, not a handoff of an unchanged design to a generic factory. A process choice affects the tools, IP, implementation decisions, and verification needed to prepare a chip for production.
- Define the product and select a process. The customer sets requirements such as performance, power, area, cost, and application. The foundry presents process options and design rules. The customer and its partners choose a suitable process, beginning a process-specific design effort.
- Prepare the design environment. The foundry works with EDA and IP partners to align software tools, libraries, PDKs, and reference flows with the process. Those resources support tasks such as circuit design, timing analysis, simulation, placement and routing, physical verification, and signoff.
- Implement and verify the chip. The customer’s engineering team, EDA providers, and any design-service partners use the process-specific resources to implement and check the design. TSMC presents its Open Innovation Platform (OIP) as a way to lower design barriers, improve cycle time, and support first-time silicon success; those are stated goals, not guaranteed outcomes for an individual design.
- Prepare for manufacturing and ramp. Once the design is ready for manufacturing, it is submitted for fabrication. The customer and foundry then work through qualification and production. The timing and contractual conditions vary by project; public descriptions do not establish one standard ramp schedule.
- Package and test the product. A finished product may need assembly and testing after wafer fabrication. For a chiplet design, this stage can also combine multiple dies—potentially made with different technologies or by different foundries—into one package.
Who else is involved, and what do they do?
Foundry partnerships rely on an ecosystem because no single company necessarily supplies every tool, design block, service, and production step a project needs. The participants and their responsibilities can overlap; there is no universal division of design ownership.
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| Participant | Typical contribution |
|---|---|
| Customer or chip designer | Defines the product, architecture, and system requirements; supplies or commissions the design; selects partners and participates in implementation and qualification. |
| Foundry | Provides process technology, manufacturing, design rules, process-specific enablement, and potentially packaging and test. |
| EDA vendors | Provide and validate software used to design, analyze, implement, verify, and sign off a chip for a particular process. |
| IP providers | Supply reusable building blocks such as libraries, memory, interface, analog, and I/O IP, often tailored to particular processes. |
| Design-service and cloud partners | Offer implementation expertise or computing resources, depending on the project and platform. |
| Assembly and test partners | Handle packaging integration, assembly, or testing when those services are not provided directly by the foundry. |
For example, TSMC’s EDA Alliance page listed Cadence Design Systems, iROC Technologies, Jedat, Keysight Technologies, Lorentz Solution, Primarius, Siemens EDA, Silvaco, SkillCAD, Synopsys, and Zuken as of September 23, 2026. Alliance membership and tool availability can change, and a listing alone does not establish that every partner’s tools support every process or project.
Why does process-specific enablement matter?
A design must be implemented and verified against the constraints of its intended manufacturing process. PDKs, libraries, IP, and validated EDA flows connect the design work to those constraints. They help engineering teams make informed implementation choices and check a design before it is sent to the foundry; they do not remove the need for project-specific design and qualification work.
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The coordination matters even more for products built from multiple dies. A chiplet package depends not only on each die but also on package design, connections between dies, and integration across the technologies involved. Intel describes packaging that can combine chiplets from different technologies and foundries. TSMC and Samsung also describe 3D or heterogeneous-integration capabilities and ecosystem support.
How do TSMC OIP, Samsung SAFE, and Intel Foundry illustrate the model?
These company descriptions show different named ecosystems for coordinating design and manufacturing resources. They are examples of what each company says its platform includes, not independent comparisons of performance or a guarantee that every capability applies to every customer.
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| Program or collaboration | What the company describes | Important qualification |
|---|---|---|
| TSMC Open Innovation Platform (OIP) | A design technology infrastructure with ecosystem partners, including silicon-verified IP and libraries, EDA certification, cloud-based design capabilities, design services, and advanced 3D stacking and packaging. | TSMC describes the platform as supporting design collaboration and first-time silicon success; that is an objective, not a promised result for an individual project. |
| Samsung Foundry SAFE | An ecosystem spanning IP, EDA, cloud, design services, and outsourced assembly and test. Samsung also describes an MDI Alliance for 2.5D/3D heterogeneous-integration packaging. | These are Samsung’s descriptions of its platform and ecosystem. |
| Intel Foundry ecosystem | A systems-foundry approach bringing together IP, EDA, process nodes, advanced packaging, and assembly and test. Intel’s fact sheet says more than 40 partners across seven alliances are active in the ecosystem. | The partner count is Intel’s own figure in its currently available fact sheet, not an independent industry-wide count. |
| Intel–UMC collaboration | The companies announced joint development of a 12 nm process platform drawing on Intel’s U.S.-based high-volume manufacturing capacity and FinFET experience, alongside UMC’s process leadership and foundry customer support. They also said they would work on design enablement with EDA and IP ecosystem partners. | The companies said production was expected to begin in 2027. That is a forward-looking target in their announcement, not evidence that production has begun. |
What should a customer compare when choosing a partnership?
A useful comparison starts with the needs of the specific chip, rather than a foundry’s ecosystem size or a process label alone. Assess capabilities against the intended design and production plan.
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- Design readiness: Are the necessary PDKs, libraries, IP, EDA tools, and reference flows available and validated for the selected process?
- Engineering support: What customer design support and implementation resources are available?
- Manufacturing and supply: What evidence is available about manufacturing quality, capacity, location, and supply resilience for the project’s needs?
- Packaging and test: Are the required advanced packaging, assembly, and test options available, either from the foundry or partners?
- Multi-die integration: If the product uses chiplets, how will package-level integration and interoperability across dies, technologies, or foundries be handled?
- Commercial and legal terms: What do the project’s actual agreements say about price, capacity commitments, IP protections, confidentiality, and responsibilities?
Public ecosystem pages can help identify stated capabilities and partners, but they do not establish a customer’s price, capacity guarantee, allocation of IP ownership, liability, or production outcome. Those points require project-specific evidence and contract terms.
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