There is no universal signaling rate or distance at which PCB copper must give way to optics. Choose an interconnect for the complete channel and system: where the link sits, how far it must reach, its lane rate and signal loss, and the power, thermal, density, serviceability, and compatibility constraints around it. The practical choices range from board traces and short copper links to near-ASIC copper, pluggable optics, and co-packaged optics (CPO); die-to-die chiplet links are a separate, package-level layer.
Start with the link’s location and job
“Copper or fiber?” is not a single system-wide decision. A data-center system contains links at several physical scales, and each may need a different medium. A board trace connects components within a system; a cable or faceplate transceiver carries a link beyond the board; and a die-to-die interface joins chips inside a package. The signaling standard alone does not select the physical architecture.
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Marvell frames within-rack connections as a potential use for copper or co-packaged copper and across-rack connections as a potential use for optics. That is a supplier’s useful design framing, not a universal taxonomy: actual systems vary in protocol, reach, topology, and packaging.
PCB and board-level electrical routing
Electrical traces route signals between components on a board and toward connectors. At higher lane rates, longer routes can make signal integrity and power harder to manage. Channel loss and crosstalk, PCB stackup and materials, connectors, equalization, and any need for retimers all affect whether a particular route works. A raw interface rate does not, by itself, establish a board’s usable reach.
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Short-reach copper cables
Direct-attach copper and active electrical cables (AECs) can serve nearby links, including some within-rack connections. Marvell describes AECs as short-reach options, while NVIDIA lists specific LinkX copper configurations for high-speed deployments. Port compatibility, cable type, reach, power, airflow, and cable congestion belong in the design decision.
Near-ASIC or co-packaged copper
Co-packaged copper (CPC) brings a copper connection closer to an ASIC or package, bypassing some board routing. Molex positions CPC as a serviceable near-ASIC approach; these are supplier descriptions, not independent comparative performance findings. The shorter electrical path must be weighed against assembly, substrate protection, manufacturing, rework, serviceability, and upgrade choices.
Pluggable optics
Pluggable optical modules place electrical-to-optical conversion at the equipment faceplate. They can carry traffic over fiber where the electrical path to a remote endpoint is unsuitable, but module type, host port, fiber arrangement, connector, reach, and cooling must match end to end. “Optical” does not mean that all modules or fiber links interoperate.
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CPO places optical components close to, or on the same substrate as, the IC. Corning describes the shorter electrical path as a way to concentrate bandwidth. It does not remove electrical-to-optical conversion or the fiber connection: fiber alignment and harnessing, package integration, thermal design, test, yield, and repairability remain important. Molex also highlights thermal isolation, testability, and assembly as CPO design concerns.
Chiplet and die-to-die links
A die-to-die link is inside a multi-die package, not a rack-network link. The Open Compute Project’s OpenHBI specification defines a high-performance chiplet interface over a silicon interposer or equivalent common-package medium, with interoperability, manufacturability, and testability among its concerns. Its role is distinct from choosing copper cable or fiber for connections between systems.
Use standards rates as context, not as a copper-to-optics threshold
PCI-SIG lists PCIe 6.0 at 64.0 GT/s raw and up to 256.0 GB/s over x16. The specification uses PAM4 and Flit-mode encoding with FEC/CRC, and PCI-SIG says it remains backward compatible. These are interface specifications; they do not guarantee that every board route can carry a given link without retimers or other channel-design measures.
PCI-SIG says PCIe 7.0 version 1.0 was released to members on June 11, 2025, at 128.0 GT/s. Its stated goals include optical interconnection between compliant silicon and extended reach across racks and pods. Those are specification capabilities and goals, not evidence that optical PCIe deployments are generally available.
The Ethernet Alliance’s 2026 roadmap covers 800G and 1.6T interfaces and discusses CPO, CPC, and linear-drive or linear-receive optics (LPO/LRO) as integration approaches in the context of data-center power efficiency. A roadmap indicates industry direction; it is not an independent benchmark of deployed performance.
Compare the architectures by where they sit
| Architecture | Typical position | What to evaluate |
|---|---|---|
| PCB electrical channel | Between components on a board and toward connectors or the front panel | Route length, lane rate, loss, crosstalk, stackup, equalization, retimers, and power budget |
| Short-reach copper cable or AEC | Within a rack or between nearby systems | Required reach, cable and port compatibility, power, airflow, and cable congestion |
| Near-ASIC or co-packaged copper | At or close to the ASIC/package | Electrical-path reduction versus assembly risk, rework, serviceability, and upgrade path |
| Pluggable optics | At the equipment faceplate for a fiber link | Reach, fiber type and count, connector, module compatibility, power, cooling, and maintenance |
| CPO or near-package optics | Optical engine adjacent to or packaged with compute or switch silicon | Electrical-path reduction, fiber routing and alignment, thermal design, test, yield, and repairability |
| Chiplet/die-to-die interface | Within a multi-die package | Package medium, bandwidth density, latency, energy per bit, interoperability, and manufacturing test |
The sources do not establish a controlled, independent comparison of cost, power per bit, reliability, thermal load, or crossover distance across these architectures. Those values depend on the implementation; do not treat a vendor’s product reach or architecture description as a universal limit or head-to-head result.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.DR4 and FR4 are different optical arrangements
NVIDIA’s LinkX page gives concrete examples of why optical labels and reach figures must be read as specific product configurations. It lists selected LACC/AEC copper options up to 2.5–3 m for XDR 2x800G and 1.6T Ethernet deployments, single-mode DR4 up to 500 m, and FR4 up to 2 km. These are NVIDIA product examples, not general maximum distances for copper, DR4, or FR4.
| Example | Fiber and connector arrangement | Example reach listed by NVIDIA |
|---|---|---|
| DR4 | Four parallel channels over eight fibers; MPO-12/APC connector | Up to 500 m for the cited single-mode product example |
| FR4 | Four wavelengths multiplexed over a fiber pair; LC connectors | Up to 2 km for the cited product example |
NVIDIA explicitly says DR4 and FR4 cannot be directly linked to each other. Check the complete optical path—including host and module compatibility, fiber topology, connectors, and channel budget—instead of assuming two modules interoperate because both are optical or share a reach category.
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- Locate the endpoints. Determine whether the connection is on one board, between packages or chips, between nearby systems, or across racks or pods. This separates board routing, package interfaces, cabling, and network links before comparing media.
- Set the actual reach and signaling requirements. Specify the protocol, lane rate, bandwidth, and physical route. Use standards rates to describe the interface, not to infer a maximum electrical distance.
- Establish the electrical channel budget. Account for traces, connectors, cable segments, loss, and crosstalk; determine whether equalization or retimers are needed. Request channel simulations and component data for the exact design rather than assuming a generic copper limit.
- Compare system constraints. Include port and link power, heat removal, density, airflow, cable congestion, and how the link will be installed, tested, serviced, or replaced. A shorter signal path may help one constraint while adding assembly or repair trade-offs.
- Verify optical compatibility where applicable. Confirm module, host, reach, fiber type and count, connector, and topology at both ends. A format name by itself is not enough to establish a compatible link.
- Assess integration maturity and lifecycle. For CPC or CPO, include package design, manufacturing test, fiber alignment, thermal placement, yield, rework, and repairability. Decide whether the density or path-length advantage fits the deployment and its service model.
- Validate the chosen implementation. Use design-specific channel analysis and vendor data sheets, and seek independent deployment evidence where it is available. The sources cited here do not establish a universal break-even distance or a cross-architecture winner on cost, reliability, or power per bit.
What the evidence supports—and what it does not
The standards and product pages establish interface rates, named architecture categories, and selected product configurations and reach examples. They do not settle the distance at which a given system should move from PCB copper to CPC, pluggable optics, or CPO. The defensible choice is therefore a channel- and system-level design decision, not a blanket rule based on one data rate or distance.
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