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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsNo. A smarter SSD controller can process selected operations, reduce copies between storage and the host, and add caching or device-local memory. It cannot replace the system DRAM or GPU HBM that AI models use for active parameters, activations, attention state and runtime data. Current AI reference systems still specify large DRAM pools alongside NVMe storage.
The short answer: storage intelligence is not working memory
An SSD is persistent storage. System DRAM and GPU HBM are working memory: processors load data into them and perform the repeated, fine-grained reads and writes required by model execution. Making the SSD controller more capable changes how data is moved or transformed; it does not turn NAND flash into a low-latency, high-bandwidth replacement for RAM.
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Three technologies are often mixed together in product descriptions:
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- Host Memory Buffer (HMB) lets an NVMe controller use a region of the host’s DRAM. The drive is borrowing system memory, not adding memory.
- Computational storage executes selected programs or data-processing operations near the flash, reducing host-CPU work and data movement.
- CXL memory expansion exposes coherent device-attached memory to a CPU. A CXL memory device can supplement DRAM, but it is a different class of hardware from a conventional NAND SSD.
These approaches can improve an AI server’s efficiency or capacity. None eliminates the need for local DRAM, and GPU workloads still need HBM or another accelerator-attached memory tier.
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Why AI needs several memory tiers
During inference or training, the active working set includes model weights, intermediate activations, attention key-value (KV) caches, tokenizer and batching buffers, communication queues and operating-system data. The processor accesses these structures repeatedly and often unpredictably. Waiting for a storage request on each access would make an otherwise parallel workload stall.
| Tier | Primary role | Persistence | Performance character | Typical AI use |
|---|---|---|---|---|
| GPU HBM | Accelerator working set | Volatile | Highest bandwidth available to the GPU; lowest practical access path for GPU kernels | Weights, activations and attention state that must be resident during a kernel |
| CPU DRAM | Host working memory | Volatile | Low latency and high bandwidth for fine-grained load/store operations | Input pipelines, orchestration, CPU-side tensors, queues and model portions not resident on the GPU |
| CXL-attached memory | Coherent capacity expansion | Volatile | CPU-addressable through a CXL link; latency and bandwidth depend on the device and topology | Larger host-side pools, tiered memory and selected capacity-bound workloads |
| NVMe NAND SSD | Persistent capacity and staging | Non-volatile | Much higher latency than DRAM, but high capacity and parallel block bandwidth | Model checkpoints, datasets, swap-like staging, caches and local scratch space |
Bandwidth figures in a vendor specification describe a transfer stream, not the latency of each individual load. AI kernels generally need both: enough bandwidth to feed parallel arithmetic and sufficiently low latency to keep that arithmetic supplied. An SSD can stream a large file efficiently while still being unsuitable as the memory behind every tensor access.
What a smarter SSD controller actually does
Every SSD controller already performs substantial work: flash translation, logical-to-physical mapping, wear leveling, bad-block management, error correction, encryption, compression in some designs, queue handling and metadata caching. More capable controllers add programmable processing or specialized accelerators.
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If data can be filtered, decompressed, searched or transformed where it resides, the host may receive only the useful result. Fewer copies reduce CPU cycles, PCIe traffic and contention in the memory subsystem. This helps when the operation is simple enough to run on the device and the reduced output is materially smaller than the input.
Offloading selected kernels
Computational storage is not a general-purpose replacement CPU or GPU. It is useful for bounded operations such as filtering records, scanning indexes, decompression, encryption or format conversion. A full neural-network training step—with changing weights, synchronization, reductions and large matrix operations—usually remains on GPUs or CPUs.
Managing device-local resources
A controller can use on-device SRAM, DRAM or other local memory for mapping tables, queues and temporary data. That memory is sized and controlled for the device’s firmware; it is not presented to the operating system as a broad pool of addressable RAM.
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Host Memory Buffer is borrowed DRAM
HMB is the most common source of confusion in consumer NVMe specifications. The NVM Express Base Specification states: “The Host Memory Buffer (HMB) feature allows the controller to utilize an assigned portion of host memory exclusively.” The same specification requires the controller to function properly when host-memory resources are unavailable.
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When HMB is enabled, the operating system reserves a portion of its own DRAM and communicates its address to the SSD. The controller can use that region for metadata or other permitted functions. The capacity remains part of the host-memory budget, and the host can lose access to it while the controller is using it. HMB therefore cannot increase the amount of RAM available to an AI runtime.
What HMB can improve
- Metadata access and mapping performance on drives with little or no dedicated DRAM.
- Consistency for some random-access workloads compared with a controller that has no memory assistance.
- Power or cost efficiency in systems where a small DRAM reservation is acceptable.
What HMB cannot do
- Provide independent RAM capacity for model weights or activations.
- Match CPU-DRAM latency or GPU-HBM bandwidth.
- Allow a system with insufficient physical memory to run a larger model as if more DRAM had been installed.
Computational Programs and Subsystem Local Memory
NVM Express has ratified command sets for computational storage. Computational Programs provides a mechanism to discover, download and execute programs on an NVM subsystem. Subsystem Local Memory (SLM) provides read, write and copy operations for memory local to that subsystem.
These commands create a standard way to describe and invoke device-side work; they do not guarantee that every SSD can run arbitrary AI code. A deployment still needs a controller with suitable compute, local memory, firmware support, host drivers and an application that can divide its pipeline into supported operations.
The Storage Networking Industry Association identifies data movement as a primary bottleneck for AI and large-scale analytics. Near-data processing addresses that bottleneck when moving the data costs more than processing it locally. The benefit is workload-specific: if an operation produces nearly as much output as input, moving it to the drive may add complexity without saving bandwidth.
Where computational storage fits
- Good candidates: data reduction before training, decompression, filtering, feature extraction, search and integrity checks.
- Questionable candidates: operations that require frequent synchronization with GPU memory or that have irregular control flow unsupported by the device.
- Poor candidates: the main matrix-multiplication and attention kernels that require GPU HBM bandwidth and mature accelerator libraries.
SNIA notes that the standards are ratified, while integrated and validated end-to-end implementations remain an ecosystem challenge. Application support, observability, firmware updates and failure recovery must be tested as a complete stack.
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CXL memory is closer to RAM—but not the same as local DRAM
Linux defines CXL.mem as coherent CPU access to memory on a CXL device. A CXL Type-3 memory device can therefore expand the addressable memory of a server more directly than a NAND SSD. The operating system and applications can place pages in that pool according to their memory policies.
CXL does not make all memory equal. The interconnect, switch topology, device controller and access pattern determine latency and bandwidth. Local DRAM remains the fastest host tier in a typical design. A CXL device may be valuable when capacity is more important than minimum latency, or when software can keep latency-sensitive data local.
A so-called CXL SSD may combine CXL memory semantics, controller compute and flash storage. The flash portion still has garbage collection, wear management and persistence behavior unlike DRAM. Software scheduling must decide which data belongs in coherent memory and which belongs on NAND.
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A 2026 arXiv study of large-language-model serving reported that a stock CXL-SSD was about three times slower than local DRAM in its tested setup. That result is not a universal specification for every CXL device; it demonstrates why topology, firmware and workload measurements matter. Capacity expansion can be useful even when it is slower, but latency-sensitive model state should not be placed there automatically.
What current AI server guidance requires
NVIDIA’s 2026 guidance for HGX H100, H200 and B200 reference systems specifies a minimum of 1.5 TB of system memory and 500 GB/s of memory bandwidth. The same guidance separately recommends 1 TB of NVMe per CPU socket for inference and 2 TB per socket for training and deep learning. The separate figures show the intended division: substantial DRAM for active computation and NVMe for persistent data, staging and checkpoints.
NVIDIA’s 2025 RTX Pro AI Factory guidance specifies 128 GB of system memory per GPU. That is system DRAM in addition to the GPU’s own memory, not an SSD capacity target. Exact configurations vary by model size, batch size, context length, number of GPUs and data pipeline, but these reference numbers make the architectural point clear.
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How to evaluate a proposed “RAM replacement”
Use the following checklist before accepting a claim that a drive can replace memory:
- Ask what is addressable. Is the advertised capacity visible as ordinary CPU or GPU memory, or is it merely flash storage and controller cache?
- Identify the memory technology. NAND, DRAM, HBM and CXL-attached memory have different latency, endurance and coherency properties.
- Check latency, not only sequential bandwidth. Request random-read latency, queue-depth conditions and tail-latency data for the access pattern your model uses.
- Measure host overhead. Determine whether the device reduces CPU work and copies or introduces driver, polling and synchronization costs.
- Verify software support. Confirm operating-system, driver, runtime and framework integration for computational programs or CXL memory policies.
- Account for persistence and recovery. Flash survives power loss when properly configured; DRAM and HBM do not. Check checkpoint frequency, data integrity and rebuild behavior.
- Check thermal and power limits. Sustained controller compute and flash garbage collection can reduce performance under long AI jobs.
- Demand workload-specific evidence. A storage benchmark cannot predict tokens per second, training throughput or model-convergence time.
Practical choices for different workloads
Running an inference server
Size GPU HBM for the model and context, CPU DRAM for batching and orchestration, and NVMe for model files, caches and logs. If the model does not fit in HBM, first evaluate quantization, tensor or pipeline parallelism, and a deliberate CPU-memory tier before attempting storage-backed paging. Storage should stage data, not serve every attention access.
Training large models
Use DRAM for input pipelines, preprocessing, optimizer state that resides on the host and checkpoint assembly. Use fast local NVMe for datasets and checkpoints. Computational storage may help with filtering or decompression, but it does not replace GPU memory for gradient and matrix operations.
Capacity-bound enterprise systems
Evaluate CXL Type-3 memory when the bottleneck is host-memory capacity and the software can tolerate non-uniform memory performance. Treat CXL memory expansion and computational NVMe as separate purchases with separate qualification tests; one does not automatically provide the other’s semantics.
Buying a conventional workstation SSD
The accurate product description is “PCIe NVMe SSD with DRAM cache” or “NVMe SSD with Host Memory Buffer,” depending on the design. Those features can improve storage behavior, but the system still needs enough CPU DRAM and the GPU still needs its own memory.
Common failure modes and fixes
The drive appears to have free space, but the model runs out of memory
Free NVMe capacity is not allocatable tensor memory. Reduce the model’s memory footprint, add DRAM or GPU memory, lower batch or context size, or use a runtime’s documented offload strategy with measured performance expectations.
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HMB is disabled and the SSD slows down
Some systems disable HMB for policy, virtualization or compatibility reasons. Re-enable it only when the platform and firmware support it, and remember that doing so consumes a portion of host DRAM. It does not increase total memory.
CXL capacity is available but performance is erratic
Inspect NUMA placement, CXL switch topology, page migration and application allocation policy. Keep latency-sensitive queues and hot model state on local DRAM; place colder or capacity-heavy data on the CXL tier after measuring tail latency.
Computational storage shows no speedup
Profile the complete path. If the device returns almost as much data as it reads, or if host-device synchronization dominates, the offload may not reduce movement. Validate firmware, driver and application support rather than relying on a sequential SSD benchmark.
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Smarter SSD controllers are valuable because they can reduce data movement, offload selected operations and improve the efficiency of persistent storage. HMB is borrowed host DRAM. Computational Programs and SLM enable device-side processing and local-memory operations, but only for supported workloads. CXL.mem offers a genuine coherent memory-expansion path, yet its performance differs from local DRAM and a CXL-SSD still includes a slower flash tier.
For AI workloads, design the hierarchy explicitly: GPU HBM and CPU DRAM hold active working sets; CXL memory can extend host capacity when its latency is acceptable; NVMe stores and stages persistent data. Any product claim that an SSD replaces system RAM should be treated as incorrect unless it is describing a separate CXL memory device and providing workload-specific measurements.
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