CUDA workloads do not move between NVIDIA, AMD, and Intel GPUs by changing one setting. CUDA, AMD ROCm, and Intel oneAPI are separate software ecosystems: their runtimes, compilers, libraries, drivers, profilers, and packaging are not binary-compatible. The practical route depends on how much of your application is framework code, custom CUDA C++, vendor libraries, distributed communication, or deployment automation.
For AMD, HIP is usually the shortest CUDA-shaped path. For Intel GPUs and standards-oriented multi-vendor code, oneAPI’s SYCL/DPC++ model is the main route, with OpenMP offload as another option. Automated converters can remove repetitive edits, but every migration still requires a clean rebuild, dependency replacement, numerical validation, profiling, and target-specific tuning.
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What actually changes when a CUDA workload moves
A GPU application is more than its kernel source. It includes host-side runtime calls, device kernels, compiler options, generated code, math and neural-network libraries, collective communication, framework binaries, drivers, containers, and deployment scripts. CUDA names and concepts may look similar to HIP or SYCL, but that similarity does not make CUDA binaries, tools, or APIs interchangeable with ROCm or oneAPI.
AMD states that ROCm and CUDA tools and APIs are not directly interchangeable and that the effort depends on the application and its dependencies. In practice, a model that uses only a supported framework operator path can require little source work, while a custom extension containing PTX, inline assembly, hand-tuned memory operations, and NCCL calls can become a multi-stage port.
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Three layers to keep separate
- Application and framework layer: PyTorch, TensorFlow, JAX, vLLM, SGLang, custom training loops, data loaders, and extensions.
- Programming model: CUDA C++ and kernels, HIP C++ kernels, SYCL/DPC++ kernels, or OpenMP target regions.
- Platform stack: GPU driver, runtime, compiler, math libraries, collective libraries, profiler, debugger, container base image, and orchestration.
A successful port aligns all three layers. Replacing a kernel API while leaving an incompatible library or container is not a completed migration.
CUDA, ROCm, and oneAPI at a glance
| Dimension | CUDA on NVIDIA | ROCm and HIP on AMD | oneAPI on Intel and supported plugin targets |
|---|---|---|---|
| Primary migration route from CUDA | Source platform | HIP and HIPIFY for supported CUDA C++ | SYCL/DPC++ with SYCLomatic; OpenMP offload is another route |
| Kernel language | CUDA C++ with CUDA runtime and driver APIs | HIP C++ runtime and kernel language designed for AMD GPUs | SYCL is ISO C++-based heterogeneous programming; DPC++ is Intel’s implementation |
| Automation | Not applicable to a CUDA-to-CUDA move | HIPIFY can translate supported CUDA constructs | SYCLomatic can convert substantial CUDA code, then emits diagnostics for manual work |
| Math and GPU libraries | cuBLAS, cuFFT, cuRAND, cuSolver, cuSPARSE, cuDNN, and related CUDA libraries | ROCm libraries and framework-specific builds; exact coverage depends on the operation and release | oneMKL, oneDNN, oneDPL, and other oneAPI components; mappings must be checked operation by operation |
| Collectives | NCCL | ROCm collective stack and framework integration | oneCCL for the oneAPI path |
| Framework availability | Broad support in mainstream AI frameworks | AMD lists PyTorch, TensorFlow, JAX, vLLM, and SGLang; use the current compatibility matrix for exact combinations | Availability varies by framework, device, backend, and release |
| Binary compatibility | CUDA binaries target the NVIDIA CUDA stack | CUDA binaries do not become ROCm binaries | CUDA binaries do not become oneAPI binaries |
| Performance expectation | Baseline for the existing deployment | Requires AMD architecture tuning and ROCm-specific profiling | Requires Intel-device tuning, or tuning for the selected plugin backend |
The table describes migration shape, not a guarantee of feature parity. A library may expose a similarly named routine while differing in supported data types, algorithm selection, synchronization behavior, or numerical results.
Choose the migration strategy before editing code
Framework-first migration
Start here when the workload stays inside supported PyTorch, TensorFlow, JAX, vLLM, or SGLang operators. Install the vendor-supported build for the target GPU, run an unmodified sample, and then test your model. This approach minimizes source changes, but custom CUDA extensions, unsupported operators, fused kernels, and third-party wheels remain the main risk.
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CUDA to HIP and ROCm
Choose HIP when the application is predominantly CUDA C++ and the destination is a supported AMD GPU. AMD describes HIP as “a C++ runtime API and kernel programming language designed for AMD GPUs.” Its CUDA-shaped design often makes mechanical translation easier than a rewrite into a different programming model.
HIP does not preserve every CUDA capability. You must inspect architecture queries, unsupported intrinsics, launch assumptions, inline PTX, device-side libraries, atomics, memory scopes, and any code that assumes NVIDIA-specific warp behavior. A successful HIPIFY pass is a starting point, not acceptance evidence.
CUDA to SYCL and oneAPI
Choose SYCL/DPC++ when Intel GPU deployment or a standards-oriented heterogeneous codebase is the goal. Intel describes SYCL as “a cross-platform abstraction layer that enables code for heterogeneous processors to be written using standard ISO C++ with the host and kernel code for an application contained in the same source file.”
SYCLomatic can automate broad portions of a CUDA conversion, but Intel documents the process as conversion, diagnostic review, manual migration, dependency installation, rebuilding, debugging, validation, and optimization. Its own guidance says CUDA API migration support is broad but not complete. Expect generated diagnostics such as DPCT messages and plan time to resolve them rather than suppressing them.
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Dual-backend architecture
If long-term operation across vendors matters, isolate device-specific code behind a stable interface. Keep framework integration, tensor shapes, scheduling, checkpoint formats, and test vectors common, while providing separate implementations for CUDA, HIP, and SYCL where needed. This costs more in build, test, and maintenance effort, but it prevents every future backend change from touching the whole application.
Migration playbook
1. Inventory every CUDA dependency
Create a machine-readable inventory before changing source. Include:
- CUDA runtime and driver calls, stream and event usage, memory allocation, unified or managed memory, graphs, peer access, and device queries.
- Kernel files, launch syntax, compiler flags, generated PTX or SASS assumptions, inline PTX, assembly, intrinsics, cooperative groups, warp-level operations, and architecture guards.
- cuBLAS, cuFFT, cuRAND, cuSolver, cuSPARSE, cuDNN, Thrust, CUB, NCCL, and any other CUDA-linked library.
- Custom framework extensions, C++ and Python bindings, wheel build scripts, and ABI assumptions.
- Framework, compiler, driver, toolkit, operating-system, container, and orchestration versions.
- Deployment scripts, environment variables, health checks, startup probes, GPU visibility settings, and rollback procedures.
Record which components are essential, optional, or used only in benchmarks. A dependency that appears in a build file but is never loaded should not drive the migration design; a dynamically loaded plugin that is absent from the source tree can be a production blocker.
2. Freeze a reproducible baseline
Run the current CUDA application with representative inputs and save the inputs, outputs, checkpoints, random seeds, and software manifest. Measure the metrics that matter for your service or training job:
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- Numerical outputs and acceptable tolerances for each model stage.
- End-to-end latency, throughput, batch-size scaling, and startup time.
- Peak and steady-state memory use, host-to-device transfer volume, and checkpoint time.
- Single-GPU behavior and distributed scaling, including collective-operation time.
- Failure behavior, retry semantics, and observability signals.
Without this baseline, a port can appear successful simply because it runs, even if it silently changes accuracy, increases memory pressure, or loses distributed throughput.
3. Freeze the target matrix
Select the exact destination GPU family and then pin the operating system, GPU driver, ROCm or oneAPI release, compiler, framework build, math libraries, collective library, Python version, and container base. Check the vendor’s current compatibility matrix before coding; support is version- and configuration-dependent.
For Intel targets, install the Intel GPU driver and the matching oneAPI components. If using oneAPI’s SYCL model on AMD or NVIDIA hardware, install the appropriate Codeplay plugin and verify its supported driver and toolkit combinations. A plugin expands the target set, but it does not make every CUDA library or framework extension portable.
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4. Port framework code first
Install the supported target build of the framework in an isolated environment. Run the vendor’s sample workload before introducing your application. Then exercise your model with the frozen test vectors.
Classify failures rather than editing randomly:
- Import or wheel failure: the framework build, Python ABI, driver, or runtime is mismatched.
- Unsupported operator: find a supported equivalent, move that operation to the host temporarily for diagnosis, or implement a backend-specific kernel.
- Custom extension failure: follow the HIP or SYCL path for that extension; do not assume a CUDA wheel can be loaded.
- Distributed initialization failure: inspect the collective backend, network interfaces, permissions, and rank configuration separately from model code.
AMD’s published framework list includes PyTorch, TensorFlow, JAX, vLLM, and SGLang, but the usable combination still depends on the current compatibility matrix and the operators your workload invokes.
5. Convert custom CUDA code to HIP
- Run HIPIFY on supported source. Use its output to identify mechanical substitutions and files requiring manual review.
- Compile for the AMD target. Replace CUDA compiler flags and architecture selections with the ROCm toolchain’s equivalents.
- Inspect device queries. Revisit warp size, shared-memory limits, cache assumptions, occupancy calculations, and architecture checks rather than preserving NVIDIA-specific constants.
- Resolve unsupported features. Replace inline PTX, vendor-only intrinsics, unsupported cooperative features, and assumptions about memory ordering with HIP or portable C++ constructs where possible.
- Replace libraries. Map each cu* dependency to the ROCm library or framework facility that actually supports your operation and data type.
- Run correctness tests before tuning. Do not optimize a kernel whose results have not been compared against the baseline.
HIP’s CUDA alignment reduces the amount of new syntax, but AMD-specific launch geometry, memory behavior, and library selection still determine performance.
6. Convert custom CUDA code to SYCL
- Run SYCLomatic on the CUDA project. Preserve the generated diagnostics and conversion report as part of the port record.
- Resolve DPCT diagnostics. Replace unsupported APIs, adjust pointer and queue semantics, and review every generated accessor, synchronization point, and USM choice.
- Install oneAPI dependencies. Select oneMKL, oneDNN, oneDPL, oneCCL, and any required runtime components instead of leaving CUDA libraries in the link path.
- Refactor kernels where needed. Convert launch configuration, shared/local memory, subgroup operations, atomics, and device selection to SYCL concepts. Generated code often needs clearer ownership and synchronization than a literal translation provides.
- Build for the destination device. Compile with DPC++ and the target’s device selector, then resolve compile-time and runtime diagnostics.
- Debug and validate. Compare outputs and race-sensitive behavior with representative tests before profiling.
SYCL’s single-source C++ model can support host and device code in one source file, but portability is not automatic. Subgroup size, local memory limits, floating-point behavior, and extension availability differ by device and backend.
Replace libraries deliberately
Library calls often determine more effort than kernel syntax. SYCLomatic documents common mappings from CUDA libraries to oneAPI components:
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|---|---|---|
| cuBLAS | oneMKL BLAS | Transpose conventions, data types, workspace, and asynchronous behavior |
| cuFFT | oneMKL FFT | Plan creation, layout, batch dimensions, and precision |
| cuRAND | oneMKL random-number facilities | Generator algorithms, seeding, stream or queue semantics, and reproducibility |
| cuSolver | oneMKL solver routines | Algorithm availability, workspace, pivoting, and error handling |
| cuSPARSE | oneMKL sparse routines | Index width, sparse format, deterministic behavior, and supported operations |
| Thrust and CUB | oneDPL and related parallel algorithms | Execution policies, temporary storage, ordering, and reductions |
| cuDNN | oneDNN where the operation is covered | Operator coverage, layout, fusion, precision, and framework integration |
| NCCL | oneCCL | Collective semantics, topology, transport, rank setup, and scaling |
These are migration targets, not drop-in promises. Preserve a small reference implementation for sensitive operations so that a faster replacement can be checked for numerical and semantic equivalence.
Build, package, and deploy the destination stack
Use isolated environments
Build the port in a clean container or virtual environment that contains only the selected driver interface, toolkit, compiler, framework, libraries, and application. Avoid accidentally finding CUDA headers or shared libraries from the host. Record the image digest or package lockfile, compiler options, device architecture, and environment variables.
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Separate host and device compatibility
A container can carry user-space libraries, but the host still needs a compatible kernel driver and device runtime interface. Validate the host driver, container runtime, device visibility, permissions, and resource limits independently. A successful build on a developer workstation does not prove that a scheduler node can launch the same image.
Keep a rollback path
Deploy the new backend beside the CUDA path until correctness and service-level metrics meet the acceptance criteria. Use versioned model artifacts, immutable images, health checks that execute a real device operation, and a configuration switch that can return traffic to the known-good backend.
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Run deterministic and randomized tests at several tensor sizes, batch sizes, sequence lengths, and precisions. Compare intermediate tensors as well as final predictions; a final output can remain plausible while an earlier layer has diverged.
- Define absolute and relative tolerances per operation. Do not use one tolerance for every reduction, normalization, convolution, and sampling step.
- Check NaN and infinity handling, overflow and underflow behavior, masking, padding, and empty-input cases.
- Test deterministic modes separately from production-fast modes. Different reduction orders can produce small floating-point differences without indicating a functional bug.
- Verify checkpoint save and restore, optimizer state, random-number streams, and mixed-precision loss scaling.
- For distributed jobs, test rank ordering, all-reduce and broadcast results, failed-rank recovery, and multi-node startup.
Intel recommends debug validation as part of the SYCLomatic workflow, and AMD recommends running a sample workload before scaling. Follow that order: prove one device and one representative case, then expand to larger models and distributed execution.
Profile and retune for the new architecture
Conversion preserves intent, not performance. Profile kernel duration, achieved occupancy, memory bandwidth, cache behavior, host-to-device transfers, launch gaps, synchronization, and collective operations with the destination vendor’s tools. A kernel that was compute-bound on one GPU may become memory-bound on another, and a library call may select a different algorithm or workspace size.
Common performance changes to investigate
- Thread-block or work-group dimensions that no longer match the hardware.
- Subgroup or warp assumptions embedded in reductions and scans.
- Uncoalesced memory access after a layout conversion.
- Extra host-device copies introduced by an incompatible tensor or USM choice.
- Synchronization inserted by a literal API translation.
- Different fused-operator coverage in the framework backend.
- Collective algorithms that do not match the interconnect topology.
- JIT compilation or first-use library planning that inflates startup latency.
Measure warm and cold starts separately, report the batch and sequence dimensions used, and keep the same acceptance inputs as the CUDA baseline. Do not describe a port as faster or equivalent without measurements on the exact target configuration.
Troubleshooting migration failures
The converted source compiles, but the process crashes at launch
Check that the binary was compiled for the installed GPU architecture, that the runtime and driver are compatible, and that no CUDA shared library is being loaded accidentally. Print the selected device and inspect dynamic-library resolution inside the deployment container.
Results differ beyond tolerance
Reduce the case to one operator or kernel, disable aggressive fusion and fast-math options, and compare intermediate tensors. Then inspect precision, reduction order, uninitialized memory, atomics, random-number generators, and unsupported assumptions about synchronization.
A custom extension is the only failing component
Build it independently from the framework. Replace CUDA-specific headers and compiler flags first, then test its C++ interface with a small harness. This separates extension errors from framework packaging or device-selection errors.
Distributed training hangs
Run a two-rank collective test before launching the full model. Verify that every process selected the intended backend, sees the expected devices, can reach its peers, and uses consistent world-size and rank settings. Compare oneCCL, the ROCm collective stack, or another supported backend with the framework’s documented configuration rather than carrying NCCL settings unchanged.
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Confirm that the workload is actually using the accelerator and not silently falling back to the host. Profile transfers and synchronization, check that optimized library paths are selected, and retune launch dimensions and data layouts. If the framework backend lacks a fused operator, a custom kernel or a different graph partition may be necessary.
How to decide between HIP and SYCL
| Choose this route when… | Why it fits | Main risk |
|---|---|---|
| HIP/ROCm | Your code is mostly CUDA C++, the target is AMD, and preserving CUDA-like concepts reduces rewrite time. | Unsupported CUDA features, ROCm library differences, and AMD-specific tuning still require engineering work. |
| SYCL/DPC++ | You need Intel GPU support, want a standards-based C++ model, or expect several heterogeneous backends. | Broader conceptual conversion, manual diagnostic cleanup, library replacement, and backend-specific optimization. |
| Framework-first | The workload uses supported operators and has few or no custom CUDA extensions. | Unsupported operators, custom wheels, and version-specific framework gaps can block deployment. |
| Dual backend | Multi-vendor operation is a long-term product requirement. | Higher build, test, documentation, and maintenance cost. |
Portability and peak performance are separate acceptance criteria. A single code path may reduce maintenance while leaving performance on the table; separate tuned backends may maximize throughput while increasing engineering cost. Make that trade explicit in the project plan.
Production acceptance checklist
- Target GPU, operating system, driver, compiler, toolkit, framework, library, and container versions are pinned.
- All CUDA runtime calls, kernels, libraries, extensions, and deployment scripts have an owner and migration status.
- Representative correctness tests pass at documented tolerances, including mixed precision and checkpoint restore.
- Single-device latency, throughput, memory, startup, and failure behavior meet agreed thresholds.
- Distributed collectives and multi-node recovery have been tested with the target backend.
- Profiling identifies no unintended host fallback, excessive synchronization, or unbounded temporary memory.
- Container startup, device visibility, health checks, logging, metrics, and rollback work on production nodes.
- The compatibility matrix, build instructions, known limitations, and backend-selection procedure are stored with the release.
Bottom line
Use HIPIFY and HIP when a CUDA C++ application is moving primarily to supported AMD GPUs and a CUDA-shaped source model is valuable. Use SYCL/DPC++ with SYCLomatic when Intel GPUs or standards-oriented heterogeneous execution is the objective, while budgeting for manual diagnostics and oneAPI library replacements. Start with a supported framework build whenever possible, isolate vendor-specific code when multi-vendor support is strategic, and treat correctness, deployment compatibility, and tuned performance as separate gates. No converter or API resemblance removes the need to rebuild, test, profile, and validate on the destination hardware.
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