Arm and RISC-V are different kinds of choices. Arm licenses processor technology and rights to use its architecture under commercial agreements. RISC-V is an open-standard instruction-set architecture (ISA): RISC-V International says the ISA itself can be used without a license fee or royalty, but a complete chip still needs a processor implementation, tools, system IP, verification, software, and engineering. The lower-cost option therefore depends on your product, shipment volume, schedule, software workload, customization needs, and ability to carry technical risk.
Do not compare an Arm core with “RISC-V” as though they were equivalent products. An ISA defines the software-visible contract; a core is a hardware design that implements that contract. You must compare a specific Arm license and implementation against a specific RISC-V core, open implementation, or in-house design.
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Start with the distinction between an ISA and a CPU core
The instruction-set architecture specifies what software can observe: instructions, registers, privilege behavior, memory ordering, exceptions, and related rules. It does not specify the pipeline, cache hierarchy, clock target, physical-design methodology, verification environment, or the rest of a system-on-chip (SoC).
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How Arm licensing is structured
Arm’s commercial offer can grant access to a defined processor design, an architecture for creating a customized CPU, or rights that generate a payment for each chip shipped. The exact rights, restrictions, support, and payment schedule come from the contract, not from the ISA name alone. Arm describes its options on its licensing overview and Flexible Access pages.
Technology Licensing Agreement (TLA)
Arm’s SEC filing describes a Technology Licensing Agreement as a fixed-fee arrangement for a specific design. This is the route to evaluate when you want a defined Arm technology package rather than the freedom to create an entirely new CPU microarchitecture. The contract determines which design, versions, deliverables, support, and permitted uses are included.
Architecture License Agreement (ALA)
An Architecture License Agreement allows a customer to create a customized CPU that complies with a specified Arm architecture, in exchange for a fixed architecture-license fee. This can provide more control over microarchitecture and differentiation, but it also transfers more design, verification, software enablement, and maintenance responsibility to the licensee. An ALA is not a promise that the resulting CPU work will be inexpensive; it changes where the work and risk reside.
Per-chip royalties and fixed fees
The same SEC filing says Arm may receive royalties based on a chip’s selling price or a fixed amount per chip. These are variable costs that scale with shipments, unlike a one-time technology or architecture fee. Your contract may combine an upfront payment with a royalty, or use another structure. Arm’s filing for the quarter ended June 30, 2025, filed August 6, 2025, describes the categories but does not publish one universal price or royalty rate for every customer.
For any Arm proposal, obtain the current quote and read the grant carefully. Confirm the permitted product families, geographic scope, term, software and design collateral, support obligations, derivative-work rights, audit provisions, minimums, and what happens when a core or architecture revision is introduced.
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What RISC-V licensing actually gives you
The ISA itself
RISC-V International describes RISC-V as an open standard and states in its FAQ that use of the ISA itself does not require a license fee or royalty. The organization also says designers are free to develop proprietary or open implementations for commercial or other uses. That freedom lets a company select an existing core, modify an implementation, release its own design, or build a processor internally.
The implementation is a separate decision
The open ISA does not hand you a finished CPU. RISC-V International explicitly notes that creating an implementation requires additional IP outside RISC-V, which may carry a fee. You may buy a commercial processor core, use an open implementation, contract an engineering team, or combine those approaches. Each choice has different verification evidence, support, maintenance, security, and schedule implications.
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Trademark and membership are distinct from ISA access
Using the RISC-V ISA and using the RISC-V trademark are separate matters. RISC-V International states that trademark use requires a license granted to its members for compliant implementations. Check the current membership, compliance, and branding rules before putting the trademark on a product, package, or marketing material. A trademark license should not be described as an ISA royalty.
Arm and RISC-V side by side
| Decision dimension | Arm | RISC-V |
|---|---|---|
| What you select | Arm technology and/or architecture rights under a commercial agreement; the grant depends on the contract. | An open ISA, followed by a choice among commercial IP, an open implementation, or a custom core. |
| ISA fee or royalty | Arm reports fixed license-fee arrangements and royalties tied to chip selling price or a fixed per-chip amount; terms vary by agreement. | RISC-V International says the ISA itself has no license fee or royalty. |
| Other technical costs | Integration, verification, software, system IP, support, and any work required by the selected Arm technology. | Commercial core or third-party IP, tools and services, or internal design, verification, integration, software, and support. |
| Customization path | An ALA is a route to a customized CPU compliant with a fixed Arm architecture; other licenses provide particular Arm technology. | The standard permits proprietary and open implementations, including bespoke designs, with corresponding ownership of the work. |
| Contract and branding | Review the commercial grant, royalties, support, derivative rights, and restrictions with Arm. | Review core-IP licenses and RISC-V trademark requirements separately; ISA access does not settle either question. |
The underlying descriptions come from Arm’s licensing materials, Flexible Access information, and SEC filing, and from RISC-V International’s FAQ, About page, and specification.
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Build a total-cost model instead of asking which ISA is cheaper
No reviewed official source establishes a like-for-like public total cost for a named workload, and no universal Arm license price or royalty rate applies to all chip designers. Use supplier quotes and internal estimates in a project model rather than repeating an unsupported dollar figure.
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A useful calculation is:
lifetime cost = upfront license or IP fees + (per-unit charges × shipped units) + engineering + verification + software + system IP + tools + support + compliance
Prepare low-, expected-, and high-volume cases. A fixed fee has a different effect at 10,000 units than at 100 million units; a per-chip royalty has the opposite pattern. Include the cost of an additional tape-out, schedule slip, or security remediation when estimating risk, but label those as scenario assumptions rather than guaranteed expenses.
Upfront and recurring payments
- Arm: model the quoted technology or architecture fee, any subscription or access arrangement, per-chip royalty or fixed per-chip amount, minimum commitments, and audit or reporting costs.
- RISC-V: set the ISA fee line to zero only for the ISA itself, then add the price of the chosen core and every separately licensed block. An open implementation may have no purchase price while still requiring substantial engineering.
Engineering and verification
Estimate staff time for microarchitecture, RTL, integration, physical design, firmware, compiler work, operating-system enablement, validation, security review, documentation, and maintenance. Verification should include simulation, formal analysis, emulation or FPGA work where applicable, compliance testing, corner-case debugging, and regression infrastructure. A vendor’s mature collateral can reduce internal effort, but the reduction must be confirmed for your exact configuration.
Software and tools
Budget for compiler and debugger configuration, board-support packages, operating-system ports, hypervisors, middleware, performance analysis, CI infrastructure, and developer training. A processor that meets the ISA requirement can still force expensive software changes if it uses different extensions, privilege features, interrupt behavior, debug interfaces, or memory attributes than your existing stack.
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System IP and integration
The CPU is only one block in a chip. Interconnect, cache coherency, memory controllers, peripherals, security monitors, cryptography, safety mechanisms, accelerators, and physical-design libraries have their own licenses and integration work. Ask whether a quoted processor package includes the collateral you need or merely the CPU RTL.
Trade-offs beyond the invoice
Schedule and execution risk
A commercial Arm core can provide a defined implementation and supplier support, while a custom RISC-V design can provide control over the microarchitecture. Neither statement proves a universal schedule advantage. Compare the actual delivery date, verification status, documentation quality, staffing plan, and maintenance commitment for each candidate.
For an open implementation, inspect issue history, release discipline, test coverage, supported tools, security disclosure practice, and who will fix defects after tape-out. For a proprietary core, ask how long the vendor supports the chosen revision and whether fixes require a new license or a redesign.
Customization and differentiation
Customization is valuable only when it improves a measured product requirement. Examples include a domain-specific extension, unusual memory behavior, safety isolation, power management, or a tightly coupled accelerator interface. Quantify the expected benefit and compare it with the cost of specifying, implementing, verifying, documenting, and supporting the change.
An architecture license can permit Arm customization within its compliance rules. RISC-V can permit a proprietary extension or a wholly different microarchitecture, subject to compatibility, ecosystem, and governance decisions. More freedom also means more responsibility for software support and future migration.
Software compatibility and ecosystem fit
Do not award a blanket maturity score to either ISA. Evaluate the exact compiler version, language features, operating systems, hypervisors, debuggers, profilers, binary packages, and third-party libraries required by your product. Check whether your application depends on optional ISA extensions, vector or matrix operations, virtualization, secure boot, real-time behavior, or deterministic interrupt handling.
Make a small software proof-of-concept before signing a long-term license. Build representative workloads, measure functional compatibility and development effort, and document every workaround. The result is specific to your stack; it is not a general ranking of Arm or RISC-V.
Supplier, governance, and lifecycle risk
Read termination, escrow, indemnity, export-control, audit, confidentiality, and liability clauses. Establish who owns modifications, who supplies security patches, how vulnerabilities are disclosed, and whether you can continue shipping if a supplier changes strategy. For RISC-V, separate the governance of the open standard from the commercial terms of a particular core vendor or services provider.
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A practical evaluation process for a new chip
- Define the product envelope. Record target performance, power, area, process node, safety or security requirements, shipment forecast, launch date, supported software, and expected product lifetime.
- Choose concrete candidates. Name the Arm core and license route, or the RISC-V core, implementation, extensions, and support package. “Arm” and “RISC-V” alone are not comparable candidate specifications.
- Request written commercial terms. Ask for upfront fees, recurring charges, per-unit royalties, volume tiers, minimums, support scope, delivery milestones, and rights to derivatives. Treat verbal estimates as non-binding.
- Inventory non-CPU IP. List interconnect, memory, security, debug, peripherals, accelerators, physical-design collateral, and verification components, identifying the supplier and license for each.
- Estimate internal work. Use loaded engineering cost and calendar time for design, integration, verification, software, documentation, compliance, and maintenance. Include hiring or training if the team lacks a required skill.
- Run a software and hardware proof-of-concept. Port representative applications, test toolchains and debuggers, integrate the candidate into a small SoC, and record defects and workarounds. Do not infer production readiness from an ISA document alone.
- Model three volume cases. Calculate low, expected, and high shipments using the actual quoted fixed and variable terms. Add sensitivity columns for a delayed launch, an extra tape-out, and a support contract.
- Score risk explicitly. Rate schedule, verification evidence, security response, supplier continuity, software availability, customization burden, and exit options. Keep these ratings separate from the monetary total.
- Set a decision gate. Approve the option only when its technical proof, contract review, total-cost scenarios, and lifecycle ownership have named owners and documented assumptions.
How volume changes the economic answer
Low-volume or rapidly changing products
For a product with modest shipments or an uncertain roadmap, a large fixed engineering program may dominate the economics. A commercially supported implementation can reduce the time your team spends creating and validating a CPU, even if the contract includes fees. Compare the cost of that support with the value of reaching market sooner; do not assume the absence of an ISA royalty makes an internal build economical.
High-volume products
At high shipment volumes, a per-chip royalty can become a major lifetime expense. A custom implementation may amortize its engineering cost over more units, but only if the design reaches production, remains supportable, and does not lose the schedule or software advantages needed to sell the product. Use sensitivity analysis rather than a single break-even point based on guessed pricing.
Products needing unusual differentiation
If the product’s advantage depends on a custom instruction, specialized security boundary, or tightly integrated accelerator, compare the value of owning that design against the cost of maintaining a nonstandard software ecosystem. A standard-compatible implementation can preserve portability, but every extension still needs compiler, operating-system, test, and documentation support.
Common mistakes and how to avoid them
- Calling RISC-V “free.” The ISA may have no fee or royalty, while the implementation and SoC can require paid IP and extensive engineering.
- Treating an Arm royalty as the whole price. Upfront rights, integration, verification, software, support, and other IP also belong in the model.
- Comparing an ISA to a finished core. Specify the actual microarchitecture, extensions, interfaces, process collateral, and support before comparing proposals.
- Using a public price from another project. Arm terms are negotiated and RISC-V projects vary widely; a figure from a different volume, geography, or product is not a current quote for yours.
- Ignoring trademark rules. ISA access and permission to use the RISC-V trademark are separate checks.
- Assuming open source removes responsibility. An open implementation can shift purchase cost into verification, security response, maintenance, and staffing.
- Making a universal performance claim. Performance depends on the specific core, implementation choices, process, memory system, compiler, and workload. The official material cited here is a licensing and architecture description, not a benchmark.
Questions to put in a licensing or IP review
- What exact architecture revision, extensions, core configuration, and deliverables are included?
- Is the payment fixed, recurring, per chip, tied to selling price, or a combination?
- Are there minimums, volume bands, reporting duties, audit rights, or geographic restrictions?
- Can we modify the implementation, create derivatives, and reuse our changes in another product?
- Which verification collateral, compliance evidence, software, debug tools, and security updates are included?
- Who owns and maintains custom extensions, patches, documentation, and ports?
- What happens if the supplier discontinues the core, changes the license, or discovers a security defect?
- For a RISC-V product, do we need a trademark license, membership, or compliance process for the way we plan to brand it?
- Which costs are excluded from the quote and must be supplied by another vendor or by our own team?
What can be concluded from the available public information
Arm’s public materials establish several commercial structures—fixed-fee technology licensing, architecture licensing for customized compliant CPUs, and royalties or fixed per-chip payments—but not a universal price. RISC-V International establishes that the ISA itself is available without a license fee or royalty and that implementations can be proprietary or open, while also warning that additional IP may carry fees.
Those facts support a disciplined comparison, not a universal winner. Select the option whose complete cost, schedule, software fit, customization value, contractual rights, and lifecycle risk match your product. The decisive evidence will be the current Arm quote or RISC-V implementation proposal together with your own engineering and volume model, not the ISA label by itself.
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