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Will It Stack? How to Check Whether Raspberry Pi HATs Share Pins

HAT+ class rules do not guarantee every Raspberry Pi HAT combination will work. Compare documented GPIO connections, firmware, power and physical fit for the exact boards.
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To tell whether two Raspberry Pi HATs can be stacked, compare their documented GPIO connections and functions, then check HAT+ class, power, software configuration and physical fit. The HAT+ specification allows one board from each of its three classes—Standard, Stackable and Power—but that rule is not a blanket guarantee that any pair of boards is electrically or mechanically compatible. A reliable compatibility agent should name the exact boards and revisions it checked, explain any pin conflicts and say when the documentation is insufficient to decide.

What does “stackable” mean under the HAT+ specification?

Raspberry Pi’s HAT+ specification says, “You can connect one HAT+ from each class to a host Raspberry Pi at a time.” The classes are Standard, Stackable and Power. In particular, a Stackable HAT+ must use only the ID pins and must not electrically connect to GPIOs 2–27. The class rule permits one board from each class, including one Standard HAT+ or legacy HAT, but does not establish that every combination will work. The setup still has to meet its power needs, and physical clearance and board-specific connections still matter. See the HAT+ specification.

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The specification also notes that Stackable HAT+s are not backwards-compatible with older firmware. Check the firmware requirements for the particular board rather than assuming the class label alone settles compatibility.

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How should an agent check whether two HATs use the same pins?

It should compare evidence for the exact models and revisions, not infer compatibility from a product name or from the fact that both boards fit a 40-pin header. For each board, the useful evidence is a vendor pin map or equivalent documentation showing electrical connections, functions and any pins explicitly marked unused.

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  1. Identify the exact boards and revisions. A result for one revision should not be generalized to another unless its documentation confirms the same connections.
  2. Compare GPIO use and alternate functions. Look for overlap in GPIO numbers and connections to I2C, SPI, serial or other buses. Distinguish a pin physically connected by board circuitry from a pin merely assigned or configured by software.
  3. Account for special pins. Include identification, reset and reserved functions in the comparison. Treat a pin documented as unused differently from one with an active connection.
  4. Check class, EEPROM and software requirements. Class membership and overlay support add useful context, but neither replaces the electrical comparison.
  5. Check power and physical assembly. Confirm that the Raspberry Pi supply can support the boards and their peripherals, and that board dimensions, header orientation, clearance and any stacking header allow the proposed assembly.
  6. Explain the evidence and confidence. Cite the applicable board documentation and identify unresolved questions. If a pin map is missing or ambiguous, report the combination as unverified rather than declaring it safe.

What can a HAT EEPROM tell you—and what can’t it prove?

At boot, Raspberry Pi firmware probes the ID_SD and ID_SC pins for a HAT EEPROM. The EEPROM can identify the board and name a device-tree overlay; the overlay supplies pin-configuration and driver information. That metadata helps the system configure supported hardware, but it is not proof that two boards have compatible electrical connections, enough power or adequate physical clearance. A successful identification or overlay load should not be treated as a compatibility test.

Why does a board-level pin map matter?

The Raspberry Pi Build HAT documentation illustrates the detail an agent should preserve. It lists GPIO0 and GPIO1 for the ID PROM, GPIO4 for reset, GPIO14 and GPIO15 for Tx/Rx, and GPIO16 and GPIO17 for RTS/CTS, which are marked unused. A useful comparison reports both the function and status as documented: it should not turn a listed-but-unused pin into an active conflict, nor overlook a reset or identification connection. See the Build HAT documentation.

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Which HATs need extra caution?

Not every GPIO add-on follows the HAT+ standard. The specification specifically identifies boards without an EEPROM, including PoE and PoE+ HATs, as outside that standard. Such boards may or may not work alongside other HAT+s; their own documentation is the relevant guide. An agent should not assign them a HAT+ class or infer compatibility from the class-count rule.

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Does a stacking header resolve a pin conflict?

No. A long GPIO extension header can make pins accessible above a fitted HAT, which may help with physical assembly, but it does not change which pins either board electrically uses. Raspberry Pi’s AI HAT+ product page lists a 16 mm stacking header among the included hardware; that is a mechanical feature, not evidence that another board’s pin use will be compatible. Consider clearance and header orientation separately from the pin comparison.

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How should an agent report its verdict?

A useful answer is specific and evidence-based, not just “compatible” or “incompatible.” It should name the board models and revisions, list overlapping GPIOs and their documented functions, note reserved or unused pins, and identify the source of each claim. It should separately describe class and firmware considerations, power requirements and physical fit. Where a vendor pin map is absent or unclear, the right verdict is that compatibility cannot be verified from the available documentation—not a confident yes.

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Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.

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