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A switched-capacitor filter uses a clock to move charge, so clock-related artifacts can reach its output. The first step is to identify what you are seeing: jitter changes sampling or charge-transfer timing and can raise noise or distortion; clock feedthrough is an unwanted clock-related component coupled to the output. Improve the clock for timing problems. Consider an output RC low-pass only when the unwanted component is outside the wanted signal band. These fixes address different mechanisms.
What “clock noise” can mean
A switched-capacitor (SC) filter is a sampled-data circuit. Its switching clock is part of the filtering operation, not merely a housekeeping signal. Consequently, clock timing, clock edges, and clock-related coupling can affect the measured output. But “clock noise” is a broad description, not a diagnosis: a discrete spur, a raised broadband noise floor, and degraded filter response point to different possibilities.
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Jitter: the timing of switching varies
Clock jitter is variation in the timing of clock edges. Since the SC filter transfers charge in relation to those edges, timing error can disturb its behavior. Analog Devices explains the symptom distinction in “Anti-Aliasing Basics Using Switch-Capacitor Filters”: “If the phase error has a random distribution, the noise floor rises; if the jitter is periodical, distortion (THD) rises.” Depending on the device and circuit, poor clocking can also show up as degraded stopband attenuation or excess passband ripple.
Jitter does not mean every narrow spectral line near a clock-related frequency is caused by timing uncertainty. A periodic spur may instead be feedthrough or coupling. Likewise, a broad rise in the noise floor is a clue, not proof, of random jitter. Compare the signal with a known-good clock and inspect the filter response as well as the output spectrum.
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Feedthrough: a clock-related component reaches the output
Clock feedthrough is an unwanted clock-related signal component at the filter output. Its frequency may be outside the band of interest, in which case it may not need additional filtering. Linear Technology’s Application Note 40 (AN40) notes that a greater ratio of clock frequency to filter cutoff makes it easier to filter feedthrough. That is a design relationship, not a guarantee that a particular output spur will be harmless.
Keep the distinction practical: timing variation calls for attention to the clock and sampling relationship; an out-of-band feedthrough component may be attenuated with a suitable post-filter. If the artifact lies inside the wanted passband, a low-pass stage that removes it may also remove wanted signal. Investigate the circuit and the selected filter’s guidance rather than assuming an RC network can solve it.
Diagnose the symptom before changing components
Start with the filter’s data sheet and the actual clock waveform at the filter input. Record the clock frequency and inspect stability, duty cycle, rise and fall times, and logic levels against the limits for the specific part. Then look at both the output spectrum and the filter’s passband and stopband response. If the output is sampled by an ADC, also establish whether the conversion timing is repeatable relative to the filter clock.
- A discrete clock-related component: check whether it is outside the wanted band and whether it changes when clock coupling or post-filtering changes.
- A broadly raised noise floor: investigate clock timing and compare against a stable clock; AN40’s particular jitter tests show that noise can change, but do not establish a universal signature or penalty.
- Unexpected ripple or weak stopband rejection: verify clock quality and check the filter’s response under the conditions specified for the selected device.
- A symptom that changes with ADC timing: test whether synchronization makes the filter output settle at a consistent time before conversion.
These observations help choose a direction; they do not identify a root cause on their own. Keep the device, clock conditions, load, and measurement bandwidth consistent when comparing results. A spectrum and a time-domain view answer different questions: frequency-domain measurements expose spurs and noise changes, while time-domain checks help reveal settling behavior.
Read the artifact in relation to the clock
Note the clock frequency, filter cutoff, wanted passband, and measured artifact frequency in the same test record. AN40’s observation about a higher clock-to-cutoff ratio is useful because it explains why some designs naturally place feedthrough where the filter or a modest output network can reject it. It does not prove that every component at, near, or related to the clock is harmless. Record whether the component moves when the clock frequency changes, whether it remains when the input signal is removed, and whether it is still present at the next circuit stage.
Use the same reference level and measurement bandwidth when comparing spectra. A spur quoted in dB relative to a 500 mV reference is not directly comparable with a noise measurement in microvolts RMS unless the reference and bandwidth are understood. This is one reason to report both a narrowband spectrum and an integrated noise result where appropriate. Keep the output load unchanged as well: an RC network and the following input can alter the amplitude and settling that the instrument sees.
Improve the clock when timing or response is the problem
Use a clock source whose stability and output characteristics suit the chosen SC filter. Verify its behavior at the filter’s clock pin, not only at the clock generator: the receiving circuit sees the waveform after any intervening routing or buffering. Follow the selected filter’s data sheet for permissible logic levels, duty cycle, edge characteristics, and other clock requirements.
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Check duty cycle and edge transitions
Analog Devices’ “Generating Switched-Capacitor-Filter Clocks” says that most manufacturers specify a duty-cycle range of 40% to 60%, and warns that a duty cycle outside the range specified by the part can impair settling. Treat 40% to 60% as general guidance, not as a universal limit. The selected device’s current data sheet is authoritative for its clock input.
Slow transitions through the clock-input threshold can make internal timing less predictable and contribute to spurs. As Analog Devices puts it, “These rising and falling edges should move swiftly through the threshold of the filter’s clock input.” The practical check is the edge at the device pin and relative to that device’s thresholds—not simply whether a generator is labelled as a clock source. Do not exceed the filter’s input ratings while trying to sharpen an edge.
Use measured examples as warnings, not predictions
AN40 illustrates how strongly a particular filter’s response can depend on clock quality. In an LTC1064-1 test, an approximately 50% jittered clock produced about 42 dB of stopband attenuation at 750 Hz; the note compares this with the cited device specification of 68 dB at 1.5 times cutoff. Its stable-clock trace performed better. This is a device- and test-specific result, not an expected loss for every SC filter or a general estimate of what a given amount of jitter will do.
In another AN40 comparison using the LTC1064-1, measured noise from 10 Hz to 1 kHz rose from 156 µV RMS to 173 µV RMS with the jittered-clock setup, which the note describes as an increase of about 11%. The low-jitter comparison is labelled less than 1 ns. These figures belong to that test setup; they do not define a universal jitter limit or predict noise in another circuit.
Analog Devices also reports a cited example in which 1 ns peak-to-peak jitter reduced a 16-bit system’s SNR from 98 dB to 91 dB. That result is an example cited in its anti-aliasing article, not a conversion rule for an unspecified filter. The effect depends on the system and conditions.
Synchronize the filter clock and ADC when conversion timing matters
If an ADC samples the SC filter’s output, a predictable relationship between the filter clock and ADC sample clock can help ensure conversion occurs after the filter output has had time to settle. Linear Technology’s AN40 recommends synchronizing them for consistent timing. Analog Devices describes a system example that shares a clock between an SC filter and ADC; its clock-generation article also explains that deriving a filter clock from a related system clock can avoid asynchronous beat-frequency artifacts in some arrangements.
Synchronization is not a substitute for adequate settling or a sound clock waveform. Establish the filter’s settling behavior and the ADC’s sampling point in the actual system. The goal is a repeatable interval between the relevant filter switching activity and conversion—not simply two clocks that happen to have related nominal frequencies.
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AN40 states: “Synchronizing the A/D and switched-capacitor filter clocks is highly recommended.” Apply that recommendation where the timing relationship is relevant, while following the requirements of the particular filter and converter. If the ADC and filter are not part of a timing-sensitive conversion chain, synchronization may not be the remedy for an unrelated output spur.
Use an output RC filter only for out-of-band feedthrough
A low-pass RC network after the filter can attenuate an unwanted component if its cutoff is above the wanted passband and low enough to reduce the component. The trade-off is fundamental: lowering the RC corner increases attenuation at higher frequencies but can also attenuate wanted signal and extend settling. The network also interacts with the filter’s output impedance and the load.
What AN40’s example demonstrates
For an LTC1064-1 example, AN40 uses a 9.64 kΩ resistor and a 3300 pF capacitor, giving a corner near 5 kHz. In that setup, measured clock feedthrough changed from about −61 dB relative to a 500 mV reference (roughly 400 µV) to about −82 dB (roughly 40 µV). The note describes this as approximately a factor-of-ten reduction. It also cautions that further post-filtering is often unnecessary when feedthrough is already outside the band of interest. These are results from that application-note example, not recommended values for an unspecified filter.
For a simple first-order RC low-pass, the nominal corner is calculated as fc = 1 / (2πRC). Use that relationship as a starting point, then evaluate the network with the actual filter output, load, and signal band. A nominal corner alone does not establish the attenuation at a spur or whether the wanted response and settling remain acceptable.
Choose the RC by the constraints that matter
- Preserve the wanted band: place the pole high enough that the desired passband is not unacceptably attenuated.
- Reduce the unwanted component: check the attenuation at the measured feedthrough frequency, not just the nominal cutoff.
- Respect the output and load: account for the filter’s output impedance and the circuit connected after the RC network.
- Check settling: confirm that the additional time constant does not prevent the output reaching the required value before a measurement or conversion.
If no frequency range separates the artifact from wanted signal, an output low-pass cannot cleanly remove one while preserving the other. No universal PCB-layout recipe is established for this case. Examine the selected filter’s data-sheet guidance and investigate clock routing, coupling, and grounding in the specific design instead of presenting an RC as a guaranteed cure.
Compare the two common remedies
| Remedy | Best match | What to verify | Main risk |
|---|---|---|---|
| Improve or replace the clock | Raised noise floor, distortion, ripple, weak stopband response, or timing-sensitive settling | Stability and jitter, duty cycle, edge speed, logic thresholds, and synchronization | A clock that looks clean at its source may still violate the filter input conditions at the device pin |
| Add an output RC low-pass | A discrete feedthrough component clearly above the wanted passband | Passband loss, attenuation at the measured spur, output loading, and settling | The network can remove wanted signal or slow the response while leaving an in-band artifact |
This comparison prevents a common troubleshooting mistake: adding capacitance to an output when the real problem is timing, or replacing a clock when a harmless out-of-band component is the only visible artifact. Measure first, then select the remedy that matches the mechanism.
Check the surrounding analog design without confusing separate problems
AN40 recommends sound analog implementation, including a linear supply or a clean switching supply where needed, proper bypassing, and attention to aliasing and band-limiting. Those are sensible checks, not evidence that every clock-related output artifact is caused by the supply. Follow the selected filter’s own recommendations for supply bypassing and signal coupling, then test changes one at a time so a result can be tied to a cause.
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Also distinguish an SC filter’s output clock feedthrough from charge injection at a SAR ADC’s switched-capacitor input. Texas Instruments’ reference-design material for an ADC input describes an RC network and filter capacitor to reduce sampling charge injection and band-limit noise; it notes that the amplifier must tolerate capacitive loading and settle adequately, and recommends C0G/NP0 capacitors for that described application. That input network is not automatically a remedy for clock feedthrough generated by an SC filter upstream.
A practical decision path
- Identify what is wrong. Measure the output spectrum and response. Decide whether the concern is a discrete clock-related component, raised broadband noise, distortion, ripple, stopband degradation, or settling.
- Verify the clock at the filter. Compare its stability, duty cycle, edge transitions, and logic levels with the specific device’s data sheet. Correct clock-source or signal-integrity problems before adding an output network.
- Check timing relationships. If an ADC samples the output, determine whether filter and sample clocks can be synchronized so conversion happens at a repeatable point after settling.
- Test whether the unwanted component is out of band. If it is, decide whether it matters to the following circuit or measurement. A component outside the band of interest may need no extra filter.
- Evaluate an RC only when the bands permit it. Calculate a candidate corner, then measure wanted-band loss, attenuation at the artifact, loading, and settling using the actual circuit.
- Recheck the whole analog path. Confirm supply bypassing, coupling, and aliasing or band-limiting requirements against the device guidance; compare results in both frequency and time domains.
Change one factor at a time and keep test conditions fixed. Otherwise, a cleaner spectrum after a clock change, synchronization, or RC addition may not reveal which mechanism mattered—or whether the wanted response was compromised.
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Before signing off a correction, capture the conditions that make the result reproducible:
- Measure the clock at the SC filter input, including frequency, duty cycle, rise and fall times, amplitude, and logic levels.
- Record the filter cutoff, clock-to-cutoff relationship, wanted passband, output load, and ADC sample timing.
- Use a stable reference input and the same analyzer bandwidth, detector settings, and integration limits for before-and-after spectra.
- Measure both a narrowband view for discrete feedthrough and a defined-band RMS result for broadband noise.
- Check time-domain settling after clock transitions and after any RC network is installed.
- Verify that a reduction in the spur has not introduced unacceptable passband attenuation, ripple, or conversion-time error.
These checks are especially important when a numerical result is being compared with a specification. AN40’s attenuation and noise figures belong to its LTC1064-1 circuit and test conditions; they should be treated as warning examples and comparison points, not acceptance limits for another part.
Frequently Asked Questions
Is every clock-related spur caused by jitter?
No. Jitter is timing variation and can raise a broadband noise floor or periodic distortion. A discrete component related to the clock may instead be feedthrough or coupling. Check whether the component tracks the clock, whether it is in or out of band, and whether a known-good clock changes it before assigning the cause.
What clock duty cycle should an SC filter use?
Use the range in the selected filter’s data sheet. Analog Devices notes that many manufacturers specify 40% to 60% as general guidance and warns that an out-of-range duty cycle can impair settling. That range is not a universal limit, and the waveform must also meet the device’s threshold and edge-speed requirements at its input pin.
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First establish that the unwanted component is above the wanted passband. Choose a pole high enough to preserve the desired signal but low enough to attenuate the measured feedthrough frequency. Then check output loading and settling. If the artifact lies inside the wanted band, a low-pass cannot remove it selectively.
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Can I copy AN40’s 9.64 kΩ and 3300 pF values?
Not without checking the actual circuit. Those values produce a corner near 5 kHz in an LTC1064-1 example and reduced feedthrough from roughly 400 µV to 40 µV there. Your filter cutoff, clock rate, output impedance, load, bandwidth, and settling requirements may be different.
Why synchronize the SC filter and ADC clocks?
Synchronization makes the interval between filter switching and conversion repeatable, allowing the output to settle before the ADC samples it. Linear Technology’s AN40 highly recommends this arrangement, and Analog Devices describes shared-clock examples. Synchronization does not compensate for a bad waveform or insufficient settling time.
What if the spur is inside the wanted passband?
An output low-pass is not a clean solution because it would also attenuate wanted signal. Investigate the selected device’s guidance and the specific design’s clock routing, coupling, grounding, and timing. The available technical guidance does not provide one universal layout fix for every in-band case.
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Is there a universal acceptable jitter number?
No. The effect depends on the filter, clock frequency, signal, and system performance target. AN40’s LTC1064-1 tests show specific stopband and noise changes under its test conditions, while an Analog Devices example reports a 1 ns peak-to-peak case for a particular 16-bit system. Neither is a universal limit.
Will a cleaner power supply always remove clock noise?
No. Proper bypassing and a suitable linear or clean switching supply are important analog practices, but they do not prove that a clock artifact is supply-generated. Check the clock waveform, coupling, and filter response while changing one factor at a time so the observed improvement has an identifiable cause.
Is the RC network at a SAR ADC input the same fix?
No. A SAR ADC input RC network can reduce sampling charge injection and band-limit noise, with the amplifier sized for capacitive loading and settling. That function is distinct from suppressing clock feedthrough generated by an upstream switched-capacitor filter. Do not transfer that remedy without analyzing the actual node.
How should I verify that a fix worked?
Repeat the same frequency-domain and time-domain measurements with unchanged input, load, bandwidth, and clock conditions. Check the discrete spur, integrated noise, passband and stopband response, and settling. A lower spur is not sufficient if the RC network attenuates wanted signal or if synchronization changes conversion timing unexpectedly.
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The Bottom Line
Separate timing error from feedthrough before modifying the circuit. Improve clock stability, duty cycle, edge quality, and synchronization when jitter or response degradation is indicated. Use an output RC filter only when a measured feedthrough component is out of band and the added pole preserves bandwidth, loading, and settling. Device-specific data sheets and repeatable measurements should determine the final choice.
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