Before committing to a semiconductor foundry, confirm that its specific process can meet your chip’s requirements, that your design flow and required IP are ready for it, and that the foundry can support your production schedule and lifecycle. Compare candidates on documented, product-specific evidence—not node names, company-wide capacity, or broad marketing claims.
Start with the chip’s requirements, not the foundry’s node name
Write down the product constraints before shortlisting processes. Include performance, power, die area, analog and RF needs, memory, voltage ranges, reliability targets, expected volumes, qualification schedule, and how long the product must remain in production. A smaller or newer logic node is not automatically a better fit: the right choice depends on the process options and the chip’s actual design requirements.
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Decide whether the product calls for a leading-edge logic process, a mature or specialty process, or a design split across multiple dies. For each candidate, check the specific process and device options, metal stack, embedded memory, analog and RF devices, high-voltage support, reliability characteristics, and design rules. Match the process’s expected production status to your qualification and sales timeline.
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Samsung’s public process portfolio describes logic technologies as well as specialty offerings such as embedded nonvolatile memory, RF, CMOS image sensors, high-voltage, and BCD processes. TSMC describes a range of advanced and mature technologies. These portfolio descriptions help identify candidates; they are not an independent, apples-to-apples comparison. Ask for validated PPA—power, performance, and area—data and design constraints relevant to your workload. Public portfolio descriptions alone do not establish comparative benchmarks.
#1 Best Overall
Can your design flow use the foundry’s PDK and ecosystem?
A process design kit (PDK) provides foundry-specific models, rules, and libraries to electronic design automation (EDA) tools. It is a core part of the design-flow commitment: a team may need to adapt tools, scripts, verification practices, and schedules when moving to a different foundry or process.
Check the exact PDK release and tool flow
- Request the PDK release intended for your project and establish whether it is for evaluation, implementation, signoff, or production.
- Confirm compatibility with the team’s EDA tools and versions, including support for design-rule checking (DRC), layout-versus-schematic (LVS), extraction, reliability, and manufacturability checks.
- Ask how updates are handled and whether a PDK change could affect the schedule or require design rework.
GlobalFoundries describes PDKs as providing models, rules, and libraries that let EDA tools account for a semiconductor process. OECD’s June 2025 semiconductor value-chain report similarly explains that PDKs align a design to process capabilities and allow EDA tools to check process rules.
Verify IP availability and support
List the standard-cell libraries, memory compilers, interface IP, and other silicon-proven IP the chip needs. Verify that each item is available and licensed for the precise process, customer, and project stage; a general ecosystem listing does not establish that a particular block is ready for your design. Confirm who helps resolve design issues and how escalations work. Samsung describes a platform that can include PDKs, libraries, IP, design support, packaging, and cloud services; TSMC describes process-proven IP and libraries through its ecosystem. Treat these as indications of platform scope, not confirmation of project-specific readiness.
Rank #2
What manufacturing evidence supports the schedule and quality plan?
Ask for process- and product-relevant evidence rather than relying on a foundry’s overall reputation. In particular, establish qualification status, reliability characterization, process variation, quality controls and change management, yield-ramp history where it can be disclosed, cycle-time distributions, lot disposition practices, and delivery performance. Define how engineering lots will be used to identify and resolve problems, and what data your team can access.
TSMC says its eFoundry Engineering Collaboration includes access to pilot lots, wafer yields, wafer acceptance test (WAT) analysis, and quality and reliability data. Its manufacturing overview describes supply assurance, capacity agility, ramping, yield, cycle time, and delivery as manufacturing priorities. These descriptions identify useful diligence topics; they do not establish the outcome of a particular customer’s design or guarantee a production result.
Do not use yield figures as a cross-foundry score unless they refer to comparable products and processes and have a sound basis. No comparable, independently audited yield figures for equivalent processes and products are established here. Seek relevant evidence under appropriate confidentiality, and negotiate measurable commitments and remedies where the parties can support them.
Rank #3
Will capacity, fab location, and continuity fit the product’s full life?
Identify the fab intended to manufacture your product and ask what capacity is planned and reserved for it. Clarify how ramp timing, volume changes, lead times, and allocation changes will be handled. Also establish the continuity plan, including whether another fab can make the product, what qualification that would require, and how changes to the plan are escalated.
Geography can affect logistics, regulatory obligations, customer requirements, and exposure to regional disruption. Evaluate the actual manufacturing location and contractual plan against those needs rather than assuming that a company’s overall footprint applies to your design.
TSMC reports more than 17 million 12-inch-equivalent wafers of annual capacity in 2025 across facilities it manages and subsidiaries, and describes facilities in Taiwan, Nanjing, Arizona, and Japan. That is a company-wide capacity figure, not a customer allocation or evidence that capacity is available for a particular product. Ask for a product-specific plan and understand what happens if it changes.
Does packaging or integration affect the foundry decision?
Include packaging in the evaluation if the product depends on chiplets, high-bandwidth memory, 2.5D or 3D integration, silicon photonics, or another advanced assembly approach. Packaging can influence performance, bandwidth, power, cost, test strategy, and schedule, so it may change which foundry and partner chain is practical.
For the proposed design, verify the supported package architecture, qualification status, capacity, thermal limits, test flow, design rules, schedule, and responsibility split among the foundry and any assembly or test partners. Samsung describes heterogeneous-integration packaging, while TSMC’s technology materials describe advanced packaging and silicon stacking. Those public descriptions do not establish that a specific option is suitable or available for your project.
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What should the project cost model and agreement cover?
Compare candidates using the same volume, schedule, yield assumptions, package requirements, and test scope. Wafer price alone does not describe the project’s economics. Build a total-cost model that includes:
- Masks, non-recurring engineering (NRE), and engineering lots.
- Wafer costs at forecast volumes, with yield assumptions stated explicitly.
- Package, assembly, test, and qualification costs.
- Required IP and EDA licenses, logistics, and inventory costs.
- The cost of schedule differences, including qualification or launch delays.
Request comparable quotes and the assumptions behind them directly from each candidate. No comparable public foundry prices or project guarantees are established here.
Review support and lifecycle terms alongside the quote. Clarify design-support availability, escalation routes, access to quality data, process-change notification, production longevity, end-of-life notice, and continuity planning. Public service descriptions can indicate possible platform scope or data access, but only the proposal and agreement establish your terms.
How should you make the final comparison?
Give every viable candidate the same design assumptions and request evidence for the same decision points. Separate what is documented or contractually committed from what is a marketing statement or roadmap intention. A practical sequence is:
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1Repair Windows errors before they cause bigger problems2Scan for outdated or missing drivers - takes under a minute3Clear out junk files and repair common Windows errors- Translate product, volume, qualification, and lifecycle needs into explicit requirements.
- Shortlist specific processes and confirm their device options and production timing.
- Validate PDK maturity, EDA compatibility, required IP, package options, and support arrangements.
- Review process- and product-relevant quality, yield-ramp, reliability, cycle-time, and delivery evidence.
- Confirm the manufacturing location, planned allocation, ramp, and continuity provisions.
- Compare total project costs and negotiate the data access, schedule, change-control, and support terms the project depends on.
Commit only when the evidence and agreement support the product’s technical needs, production plan, and lifecycle. If a critical item remains an assumption—such as IP readiness, capacity allocation, or package availability—treat it as an unresolved project risk rather than as a capability already secured.
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