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Manufacturing photonic chips at scale takes more than making wafers: it requires a platform-specific process, designs built for a foundry’s process design kit (PDK), repeatable fabrication, efficient testing, and packaging that connects each chip to light, electronics, power, and heat management. Silicon photonics is one important route—not a synonym for every photonic chip—and a production-ready wafer flow does not guarantee economical finished modules.
What “at scale” means for a photonic chip
A photonic integrated circuit (PIC) guides or processes light through components such as waveguides, splitters, modulators, and detectors. A PIC becomes a usable product only when its optical and electrical signals can enter and leave the chip reliably, and when its package supports the required control, power, and thermal conditions.
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That makes scale an end-to-end manufacturing measure. Wafer capacity matters, but so do the number of dies that meet optical specifications, the speed and cost of testing them, assembly yield, and the throughput of the finished module. The Silicon Photonics chapter of the 2024 Integrated Photonic Systems Roadmap International (IPSR-I) describes mature silicon-on-insulator PIC processes on 200 mm and 300 mm wafers. Wafer diameter alone, however, does not establish production readiness.
How the manufacturing chain works
1. Choose a platform and process
The first decision is the material system and the device types the product needs. Silicon-on-insulator is a prominent platform, but different materials and devices require different process flows. For example, a design that needs a detector or light source may require integration steps beyond the core silicon photonics process. There is no single recipe that applies to every PIC.
Platform selection should reflect the intended application and the foundry process available to manufacture it. The 2024 review “Roadmapping the Next Generation of Silicon Photonics” discusses challenges including germanium detector integration, epitaxy, and laser integration. These are platform and application considerations, not steps every silicon photonics chip must use in the same way.
2. Design to the foundry’s PDK
A process design kit translates a foundry’s manufacturing capabilities into design rules and characterized building blocks. Designing against that kit helps ensure that layouts, component choices, and optical and electrical interfaces are compatible with the target process. A design that works in simulation but falls outside the foundry’s rules—or depends on uncharacterized components—may be difficult to transfer reliably into production.
PDK maturity and process control affect how well a design can be reproduced, and therefore influence throughput, reliability, yield, and cost. IPSR-I describes an ecosystem of eight CMOS foundries, four integrated device manufacturers, and approximately 20 research institutes in its 2024 chapter. Those are roadmap-reported ecosystem counts, not a live census of the industry.
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1Scan for outdated or missing drivers - takes under a minute2Repair Windows errors before they cause bigger problems3Fix the driver behind crashes, sound loss and screen glitches3. Fabricate with controlled variation
Foundry fabrication turns a PIC layout into patterned material layers and devices on a wafer. The manufacturing challenge is not simply to make the features; it is to control variation so circuits across wafers perform within their optical and electrical specifications. Small differences can affect properties such as waveguide behavior or the performance of active components, making process control and manufacturing-aligned models important to repeatability.
Yield, integration level, performance, cost, and throughput are linked. IPSR-I uses greater than 90% good-die yield as a manufacturing scaling target; it is a roadmap metric, not a universal achieved yield for current photonic chip production. A high wafer count cannot compensate for inconsistent performance or a large share of dies that fail their specifications.
4. Test wafers and identify good dies
Testing before packaging can prevent the cost and time of assembling chips that will not meet specifications. Wafer-level optical testing checks dies while they are still on the wafer, and known-good-die selection allows assembly to focus on chips that pass the relevant tests. The IEEE Electronics Packaging Society’s 2023 Heterogeneous Integration Roadmap, Chapter 9, identifies wafer- or panel-level silicon photonics testing and known-good-die approaches as development needs.
Optical testing is more complicated than checking an electrical contact: the test setup must couple light into and out of a device, and do so with enough speed and repeatability for manufacturing. Parallel testing can help throughput, but the appropriate approach depends on the chip and its optical interfaces. Intel describes wafer-scale testing and laser burn-in as features of its own silicon photonics platform; that is a vendor-specific example, not a description of every foundry’s flow. Intel also reports that its platform has shipped more than 8 million PICs and more than 32 million on-chip lasers since 2016. These are Intel’s platform shipment figures, not independent industry totals. See the company’s Silicon Photonics page.
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5. Package and connect the chip
Packaging creates the interfaces that let a PIC function in a product. It must connect optical paths to fibers or other photonic components, connect electrical signals and power, and address control and heat dissipation. Placement and attachment need to be sufficiently precise and reliable for the product’s optical performance and operating conditions.
Packaging is not an afterthought to wafer fabrication. SEMI’s page for the Heterogeneous Integration Roadmap reproduces this description of the roadmap’s scope: “Packaging is the final manufacturing process transforming devices into functional products for the end user.” The SEMI roadmap page frames why packaging belongs in the manufacturing chain.
The INEMI Integrated Photonics roadmap identifies practical packaging concerns including interconnect pitch, heat dissipation, warpage, reliability, high-precision optical placement, fiber attachment, and module assembly. Each can affect product performance or manufacturing yield. The right package route depends on the intended application and the number and type of optical and electrical connections it needs.
6. Synchronize module production
After packaging, modules still need to be assembled and tested as complete systems. A production line is limited by its slow or costly stages: high wafer output does not create high finished-product throughput if optical testing, fiber attachment, or module assembly cannot keep pace. The Intel platform page and the 2026 MIT Microphotonics Center overview of IPSR-I are useful context for treating package and test capacity as system-level scaling concerns, rather than assuming wafer capacity tells the whole story.
Where the manufacturing bottlenecks appear
- Platform integration: Some device needs, including detectors or lasers, may require integration approaches beyond the base process. The material system and application determine which steps are relevant.
- Variation and yield: Devices must meet optical performance requirements consistently across dies and wafers. Process control, suitable models, and a mature design-to-foundry flow help address this challenge.
- Test economics: Optical access and test throughput determine how efficiently manufacturers can find and select good dies before assembly. Poor screening risks spending downstream package cost on failing chips.
- Package performance and assembly: Optical alignment, fiber attachment, electrical interfaces, thermal management, warpage, and reliability all have to work together. Packaging choices therefore affect both product performance and assembly yield.
- End-to-end throughput: A bottleneck in testing or module assembly can constrain output even when wafer fabrication has capacity. Scale has to be assessed across the complete production chain.
How to judge whether a production route can scale
When comparing foundry or manufacturing options, evaluate the whole flow rather than choosing by wafer size alone. Useful questions include:
- Platform fit: Does the material and process support the devices and performance the application requires?
- Foundry readiness: Is there a suitable PDK, characterized building blocks, and process control to support a repeatable design transfer?
- Yield and reliability: How are performance variation and good-die yield measured, and under what conditions? Are the results representative of the intended production flow?
- Test strategy: Can optical tests be performed at wafer or panel level, with enough access and parallelism to support the desired throughput? How are known-good dies selected?
- Packaging route: Can the process deliver the required fiber coupling, optical and electrical I/O, thermal handling, assembly yield, and reliability?
- System economics: What are the combined costs and throughput limits for fabrication, testing, packaging, and module assembly?
Programs and institutions also help build manufacturing capabilities. For example, the U.S. Department of Defense profile of AIM Photonics documents a U.S. manufacturing innovation institute focused on integrated photonics. Such ecosystem activity is distinct from proof that any one process or package route meets a particular product’s volume, cost, or yield target.
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