Silicon-on-insulator (SOI) is a semiconductor wafer structure in which a thin layer of device-grade crystalline silicon sits above an insulating layer—usually silicon dioxide—and a supporting silicon wafer. The insulating layer, called the buried oxide (BOX), electrically separates devices in the top silicon from the underlying wafer.
What does silicon-on-insulator mean?
In a conventional bulk-silicon wafer, device regions are formed in silicon connected to the body of the wafer. In an SOI wafer, device regions are formed in a thin silicon layer separated from the supporting wafer by an insulator. That isolation changes electrical coupling and parasitic capacitance paths compared with bulk silicon; the effect on a finished chip depends on its device design and process.
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SOI describes the substrate architecture, not one specific transistor, chip, or manufacturing recipe. A useful overview of the structure and device effects is available from IEEE; Toshiba also explains the contrast between oxide isolation in SOI and pn-junction isolation in bulk devices at Toshiba’s semiconductor FAQ.
The typical SOI layer stack
- Device silicon: the thin crystalline silicon layer in which transistors or other devices are fabricated.
- Buried oxide (BOX): the insulating layer, commonly silicon dioxide, that separates the device layer from the wafer below.
- Handle wafer: the supporting substrate, typically silicon, beneath the BOX.
How do FD-SOI and PD-SOI differ?
Fully depleted SOI (FD-SOI) and partially depleted SOI (PD-SOI) describe different device-body electrostatics. The distinction is whether depletion spans the thickness of the silicon body under the relevant operating conditions.
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| Device type | Silicon body and depletion | What the label means |
|---|---|---|
| FD-SOI | The device silicon is sufficiently thin for depletion to extend through the body under relevant operating conditions. | A fully depleted device regime; it is not a blanket rating that an SOI wafer or chip is superior. |
| PD-SOI | The device silicon is thicker, so depletion does not extend through the entire body. | A partially depleted device regime, with different body behavior from FD-SOI. |
These terms describe device dimensions and behavior, not simply two wafer quality grades. When comparing implementations, also consider BOX thickness, handle-wafer properties, thermal behavior, body control, and the requirements of the intended application. BYU’s cleanroom reference discusses SOI substrates and fabrication approaches at BYU Cleanroom.
How is an SOI wafer made?
SOI is an engineered wafer structure that can be produced by several routes. Common methods include bonding and thinning, oxygen implantation, and ion-implantation-assisted layer transfer.
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- Wafer Pattern May Vary from the Product Images. Great to be used as gift, display object, exhibition, educating demonstration, testing, decoration or your collection
- Beautiful microchip pattern structure made by the advanced copper technology
- 90~130nm minimum microchip feature Copper Characterization with TEOS or Black Diamond Low-k ILD on the single crystal silicon wafer
- The original value of un-polished wafer is above $500
- No guarantee for research and other applications
- Bonding and thinning: bond silicon wafers and thin and polish one wafer to leave the device layer above the insulating layer.
- SIMOX: implant oxygen into silicon and anneal it to form a buried oxide layer.
- Smart Cut: use implantation to define a layer-transfer plane, then bond and transfer a thin crystalline silicon layer.
Soitec describes its own Smart Cut™ process this way: “Smart Cut™ technology is based on the combination of light ion implantation and molecular adhesion bonding to transfer ultrathin single crystal layers from one substrate to another.” This is a description of Soitec’s process, not a definition of every SOI manufacturing method. See Soitec’s Smart Cut technology overview.
Why use SOI, and what are its trade-offs?
The buried insulator separates device regions from the substrate, reducing certain parasitic electrical paths and substrate coupling. Those changes can matter for capacitance and device behavior, but they do not guarantee a universal improvement in a chip’s speed or power consumption. Outcomes depend on the process, circuit, and operating conditions.
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- 5 x 5 inches, 0.67 ounces, 0.03 inches thick. Some wafers are marked with alignment marks.
- The pattern is produced by light diffraction, and its reflective appearance changes with the viewing angle.
- Silicon wafers are fragile—please handle with care.
- Circuit details can be examined under a microscope.
In FD-SOI, the structure can support body-bias control: adjusting the body bias provides a way to dynamically control transistor behavior in processes designed for it. STMicroelectronics describes body-biasing as a feature of its FD-SOI technology at ST’s FD-SOI overview. It is a design capability, not a promise of a specific chip-level result.
The buried oxide also changes heat flow through the structure. Body behavior is another consideration: partially depleted devices can exhibit floating-body effects. The significance of thermal and body effects varies with the architecture and implementation, so neither should be treated as an identical penalty in every SOI device.
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- Multiple Diameter Options: Available in multiple diameters including 1, 2, 3, 4, 5, 6 and 8 inch silicon wafers
- Durable Substrate Design: Flat and solid silicon substrate supports cutting, polishing and controlled experimental handling
- Research and Educational Applications: Commonly used in laboratories, universities, research institutes and educational environments
- Precision Polished Wafer Surface: Manufactured with smooth and stable wafer surfaces, available in SSP (Single Side Polished) and DSP (Double Side Polished) configurations for sample preparation, handling, and laboratory processing.
- Wide Laboratory Applications: Commonly used in universities, research institutions, material science laboratories, and scientific training programs for silicon material studies and experimental demonstrations.
Where is SOI used?
SOI is not one application platform. Suppliers describe different SOI variants for different needs; examples include:
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- RF-SOI: wireless connectivity and radio-frequency front ends, where substrate isolation is relevant to circuit design.
- FD-SOI: low-power digital and other applications, with supplier examples that include smart devices, automotive radar, processors, RF, and mmWave.
- Photonics SOI: substrates for photonics and optical networking.
These are examples of supplier product uses, not claims that every SOI wafer is suitable for all of them. Soitec outlines its product platforms at Soitec’s product page. STMicroelectronics separately describes a particular memory technology combining FD-SOI with embedded phase-change memory for automotive, industrial, and aerospace applications; that scope applies to the named technology, not FD-SOI in general. See ST’s FD-SOI overview.
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How to compare SOI implementations
The name SOI alone does not identify the device behavior, substrate properties, or suitability for a design. Compare the specific implementation against its requirements:
- Depletion regime and device-layer thickness: determine whether the design uses FD-SOI or PD-SOI and what electrostatic control it needs.
- BOX and handle wafer: check the insulating-layer design and supporting substrate specified for the process.
- Application needs: assess whether the priority is RF isolation, digital operation, photonics, or another specialized use.
- Thermal and body behavior: account for the way the structure affects heat flow and body coupling in that particular device.
There is no reliable universal percentage by which SOI is faster or lower-power than bulk silicon. The electrical changes are real, but a performance claim needs a defined device, process, workload, and comparison basis.
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