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What Is Hardware Virtual Memory? How the MMU Maps Addresses

Hardware virtual memory lets a processor’s MMU translate software-visible virtual addresses into physical addresses using mappings managed by the operating system.
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Hardware virtual memory is the processor-supported translation of software-visible virtual addresses into physical addresses. The processor’s memory management unit (MMU) uses mappings that the operating system maintains, allowing programs to work with their own address spaces rather than the machine’s physical memory layout.

What hardware virtual memory means

When a program accesses memory, it uses a virtual address. A physical address identifies a location in the machine’s memory system. In a paged system, the MMU translates between the two using page mappings set up and managed by the operating system.

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The Linux kernel defines the MMU as hardware that handles virtual-to-physical address translation. Linux kernel documentation: Page Tables

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How the MMU translates an address

  1. The program issues a virtual address. In a paged system, it consists of a virtual page and an offset within that page.
  2. The MMU checks the TLB. A translation lookaside buffer (TLB) caches recent address translations. If the needed mapping is there, the processor can reuse it without another page-table lookup.
  3. The processor looks up a missing translation. On a TLB miss, the translation mechanism consults page tables, often through a hierarchical page-table walk. Some architectures also cache page-walk information.
  4. The mapping selects a physical page. A valid mapping identifies a physical page frame; the virtual address’s offset selects the location within that frame.
  5. The system checks access rules. The hardware can enforce permissions and memory attributes associated with a mapping. If the mapping is unavailable or the access is not permitted, the processor raises a fault for software to handle.

Page tables are data structures, not the MMU itself. The operating system establishes and changes mappings and handles faults; the hardware performs translation and applies relevant checks. Details such as table format, page-walk levels, and TLB maintenance vary by architecture. Arm: Learn the architecture — AArch64 memory management Guide

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How virtual memory differs from physical memory

Virtual memory is the address-space abstraction software uses; physical memory refers to locations in the machine’s memory system. Virtual addresses let processes use logical address spaces without needing application code to know the physical memory map. The operating system can use mappings to isolate processes, enforce access permissions, and share selected mapped data.

A virtual address does not necessarily have a page currently resident in RAM. The operating system may keep only needed pages in physical memory and arrange for a page to be made available when accessed. Virtual memory therefore does not mean that every address is continuously backed by RAM. Linux kernel documentation: Concepts overview

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What a page fault means

A page fault occurs when an access lacks a usable mapping, violates its permissions, or refers to a page that is not currently resident. The operating system handles the fault according to its cause: it may make a page available and update mappings, or reject the access. A page fault is not automatically a program error; it can be part of ordinary demand paging. The precise handling depends on the operating system and architecture. Apple Developer Documentation: About the Virtual Memory System

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Which details depend on the processor architecture

The basic idea—translating virtual addresses using operating-system-managed mappings—is common, but implementations differ. Translation stages, page sizes, page-table organization, TLB behavior, invalidation requirements, and permission checks are architecture-specific. For example, AMD’s Zynq-7000 technical reference manual describes that product’s MMU, translation tables, table walker, and TLB; those implementation details should not be treated as universal properties of all processors. AMD: MMU Functional Description, UG585

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