Extreme ultraviolet (EUV) lithography projects circuit patterns onto silicon wafers with 13.5-nanometer light. That very short wavelength lets chipmakers print the most intricate layers of leading-edge logic and memory chips with fewer repeated patterning steps than some deep-ultraviolet (DUV) alternatives.
EUV is not a replacement for every other lithography method. A modern chip uses a mixture of EUV, DUV and mature processes, selected layer by layer. Most chips do not need EUV at all; its value appears when a design requires extremely fine features and the fab can justify the equipment, process complexity and operating cost.
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What EUV lithography means
Lithography is the patterning stage of semiconductor manufacturing. A lithography tool projects a circuit image onto a wafer coated with a light-sensitive material. The exposed pattern becomes a template for later manufacturing steps, allowing transistors, wiring and other structures to be built in precisely aligned layers.
EUV stands for extreme ultraviolet. The systems used for chip production operate at a wavelength of 13.5 nanometers. ASML describes that wavelength as more than 14 times shorter than the light used by DUV lithography. A shorter wavelength gives the optical system another route to resolving smaller pattern details, although final capability also depends on numerical aperture, masks, resist behavior, alignment, process control and yield.
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The practical consequence is selective use: EUV is aimed at the hardest-to-print layers of advanced chips, while DUV and mature lithography handle many other layers. Calling a chip advanced does not mean every layer was exposed with EUV.
How an EUV exposure is made
1. Tin droplets become a light source
An EUV tool starts with a stream of fast-moving tin droplets. Laser pulses strike the droplets and create a hot plasma. That plasma emits EUV radiation at the wavelength needed for chip patterning. This is a laser-produced-plasma source, rather than a conventional lamp.
Source power matters because each wafer exposure needs enough usable light to support practical productivity. In its 2025 annual report, ASML described a 1,000-watt EUV light-source demonstration in April 2025. That is a vendor-reported demonstration milestone, not a statement that every production system operates at 1,000 watts.
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2. The light travels in a vacuum
Air absorbs EUV light, as do most ordinary optical materials. Consequently, the exposure path is maintained at high vacuum. The vacuum is not an optional performance setting; it is a basic condition for getting the light from the source to the wafer without losing it to the atmosphere.
3. Mirrors replace ordinary lenses
Because conventional lenses would absorb EUV, the system uses multilayer mirrors. These mirrors guide and focus the light through the tool. Their surfaces and coatings must be extremely controlled because every reflection affects the small amount of light available for exposure.
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4. A patterned reticle carries the circuit image
The EUV beam reflects from a patterned reticle, the semiconductor equivalent of a mask. The projection optics reduce the reticle image by a factor of four before it reaches the wafer. The reduced pattern is then aligned with structures already printed on the wafer.
5. The wafer receives one layer of the design
The tool exposes a selected layer, not an entire finished chip in one pass. The wafer proceeds through additional coating, exposure, development, etching, deposition, cleaning and alignment steps as the complete three-dimensional structure is built. EUV is therefore one stage in a long manufacturing flow, not a standalone way to fabricate a chip.
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Why a shorter wavelength helps
Lithography must distinguish adjacent lines and spaces while preserving their intended dimensions across a large wafer. Shorter-wavelength light makes finer pattern projection possible in principle. Numerical aperture, abbreviated NA, describes how much of the available light cone the projection optics can collect. Increasing NA can improve stated resolution, but it also changes the optical design, exposure field and process requirements.
This is why EUV capability cannot be reduced to wavelength alone. A 13.5-nanometer source does not mean a chip contains 13.5-nanometer transistors, nor does a tool’s resolution specification define a commercial process node. The numbers describe different things:
- Wavelength: the color, or physical period, of the exposure light.
- Numerical aperture: an optical property that influences how finely the system can resolve patterns.
- Stated resolution: the tool specification for the patterns it is designed to resolve under specified conditions.
- Process node: a foundry’s manufacturing-generation label, which is not a direct conversion of wavelength or tool resolution.
EUV and DUV work together
DUV remains essential because a chip contains many layers with different patterning demands. Some layers have relatively large features and do not justify EUV exposure. Other layers may be printed with DUV using established processes. Mature lithography can produce a wide range of chips whose designs do not require the smallest leading-edge features.
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For particularly dense layers, DUV can use multiple patterning: the design is split across repeated exposures and process steps. EUV can reduce the need for some of those repetitions by printing a more complex pattern in fewer exposures. That does not make EUV automatically cheaper. The relevant comparison includes tool productivity, mask and process complexity, defect rates, alignment effort, wafer yield and the cost of operating the fab.
| Question | EUV role | DUV or mature-lithography role |
|---|---|---|
| Which layers? | The most intricate layers of selected leading-edge logic and memory products. | Many other layers, including layers with less demanding feature sizes. |
| Why use it? | Short-wavelength patterning and the potential to avoid some repeated exposures. | Established production capability for a broad range of feature sizes and products. |
| Is it needed for every chip? | No. Many chips do not require EUV. | Yes, DUV and mature tools remain part of advanced and mainstream manufacturing flows. |
| Does it define a node? | No. Tool wavelength and resolution are not transistor dimensions or node names. | No. The same distinction applies to DUV specifications. |
Current EUV system generations
Two EUV platform categories are important in current product descriptions. Their specifications are vendor-stated system capabilities, not claims about the dimensions of every chip made with them.
| Platform | Numerical aperture | Stated resolution | Intended use | Manufacturing status in the cited material |
|---|---|---|---|---|
| NXE EUV systems | 0.33 NA | 13 nm | Production patterning for leading-edge logic and memory layers. | Established EUV platform described in current product information. |
| EXE High-NA EUV systems | 0.55 NA | 8 nm | Future advanced logic and memory manufacturing requiring higher resolution. | Product-page positioning and rollout information are vendor roadmap statements; they should not be treated as independent confirmation of production adoption. |
High-NA EUV increases the numerical aperture from 0.33 to 0.55 in these platform descriptions. The resulting 8-nanometer and 13-nanometer figures are stated system resolution specifications. They are not transistor sizes, guaranteed dimensions for every layer or alternative names for process nodes.
Why chipmakers accept EUV’s complexity
Fewer repeated patterning operations on critical layers
When a dense layer is difficult to print with DUV, multiple patterning may divide the work into several exposures and intervening process steps. EUV can consolidate some of that work. Fewer repetitions can simplify alignment and reduce opportunities for process variation, although the benefit depends on the exact layer and manufacturing flow.
Access to leading-edge density
Advanced processors, memory devices and other high-density products compete on how much useful circuitry can fit into a given area and how efficiently it operates. EUV gives manufacturers an optical tool for the most demanding layers when older approaches become too repetitive or difficult to control.
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Economics are a complete-flow question
An EUV scanner is specialized capital equipment, and its value cannot be judged by purchase price or by counting exposures alone. Manufacturers weigh source power, uptime, wafer throughput, mask costs, defect inspection, process steps, maintenance, alignment and yield. A layer that needs fewer exposures may still be expensive if productivity is low or defects reduce usable wafers.
ASML identifies productivity and cost efficiency as continuing goals. Its 2025 annual report quotes Jayson Stewart, Head of Source Research: “For a long time, the output wasn’t powerful enough to make EUV a viable investment for customers.” The statement explains why source development has been central to commercialization; it does not promise a universal cost saving for every chip or fab.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What makes EUV difficult to deploy
Generating enough usable light
The source must repeatedly convert laser energy and tin droplets into usable EUV radiation. More source power can support productivity, but increasing power also places demands on droplet delivery, debris control, optics, cooling and system reliability. A laboratory or demonstration milestone therefore cannot be read as the normal operating condition of every installed tool.
Maintaining a clean optical path
Vacuum operation prevents air absorption, while multilayer mirrors provide the necessary reflection and focusing. Contamination or mirror degradation can reduce the light reaching the wafer and affect maintenance intervals. The vacuum environment and reflective optics make EUV fundamentally different from lens-based optical systems.
Controlling defects and alignment
Critical layers must align with patterns already present on the wafer. Reticle defects, particles, focus variation and overlay errors can lower yield. EUV removes some repeated DUV exposures, but it does not remove the need for inspection, metrology and tight process control.
Integrating EUV into a mixed-tool fab
A fab does not replace all of its lithography equipment with EUV. Engineers decide which layers benefit from EUV and which are better served by DUV or mature tools. The result is a coordinated flow in which masks, resist processes, etch conditions, deposition steps and inspection systems all have to work together.
When a chip does not need EUV
Many products use larger features, less dense interconnects or established process generations. Automotive controllers, power-management devices, sensors, connectivity chips and numerous industrial components can be manufactured with mature lithography when their designs do not demand leading-edge patterning. The absence of EUV does not indicate that a chip is poorly made; it reflects the requirements and economics of its design.
Even an advanced chip may contain layers that are economical to print with DUV. EUV is reserved for layers where its resolution and process advantages justify the added complexity. This layer-by-layer selection is the key to understanding why EUV and DUV coexist.
How to interpret EUV claims and specifications
- Check whether a number describes wavelength, numerical aperture, resolution, source power or a process node; these are different measurements.
- Ask whether the figure is a vendor specification, a demonstration milestone or an independently verified production result.
- Look for the measurement date and product generation. The cited NXE and EXE figures come from current product information accessed on October 13, 2026.
- Do not infer that every layer of a chip uses EUV simply because the chip is described as leading edge.
- Treat roadmap language about future systems as a supplier’s plan unless independent manufacturing evidence confirms deployment.
- When comparing cost, include yield, defects, productivity and all process steps rather than assuming fewer exposures automatically mean lower wafer cost.
The practical answer for chipmakers
Chipmakers need EUV because some leading-edge layers are too dense or too repetitive to pattern efficiently with older methods alone. EUV’s 13.5-nanometer light, generated from laser-struck tin droplets and guided through vacuum mirrors, provides a way to resolve those patterns with fewer multiple-patterning operations in suitable cases.
They do not need EUV for every product or every layer. The production decision is a technical and economic optimization: use EUV where its resolution and potential process simplification outweigh the cost and complexity, and use DUV or mature lithography everywhere else that meets the design requirements.
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