An AMD Matrix Core is a GPU execution unit built to accelerate matrix calculations used in AI, high-performance computing (HPC), and dense linear algebra. AMD’s ROCm documentation also calls these units MFMA units, short for matrix fused multiply-add. They are part of supported AMD GPU architectures—not separate processors or add-in cards—and what they can do depends on the GPU generation, data type, and software.
What does “AMD Matrix Core” mean?
AMD uses “Matrix Core” for specialized GPU hardware that performs large matrix operations. In ROCm’s hardware glossary, the units are identified as Matrix Cores (MFMA units), and AMD describes their role as executing matrix work in a single instruction for AI and HPC workloads. AMD ROCm hardware glossary
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The “core” is an execution capability inside a GPU, not a CPU-like processor or a standalone component. AMD’s HIP hardware documentation says CDNA architectures beginning with MI100 include specialized matrix-acceleration units. These can execute independently of vector ALU operations, allowing matrix and vector work to overlap. AMD HIP hardware implementation documentation
What does MFMA do?
MFMA means matrix fused multiply-add. The operation can be represented as D = AB + C: multiply matrices A and B, then add matrix C to the result. Rather than having each GPU lane handle only an isolated scalar operation, an MFMA instruction works on a matrix fragment whose input and output elements are distributed among the lanes of a wavefront and held in their vector registers. AMD HIP hardware implementation documentation AMD’s Matrix Core programming explanation
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This wavefront-wide arrangement is what lets one instruction carry out a substantial piece of matrix work. It is still a GPU instruction executed by the GPU’s hardware; “one instruction” does not mean an entire AI model or application completes in one step.
What are AMD Matrix Cores used for?
Matrix Cores are intended for workloads with substantial matrix math, including generalized matrix multiplication (GEMM), dense linear algebra, AI, and HPC. GEMM is a common building block in neural-network operations and scientific computing, which is why matrix acceleration can matter in those fields. AMD ROCm hardware glossary AMD’s Matrix Core programming explanation
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Having Matrix Cores does not guarantee a particular application will run faster by a fixed amount. The result depends on factors such as the GPU model, matrix dimensions, supported precision, software implementation, and memory behavior. A library or application may not use MFMA for every operation.
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Most users do not issue MFMA instructions directly. Libraries can select and launch optimized kernels when the operation and GPU support make them appropriate. AMD identifies rocBLAS and rocWMMA as higher-level ways to work with matrix acceleration; developers seeking closer control can use compiler intrinsics. AMD’s Matrix Core programming explanation
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AMD also notes that Matrix Core-accelerated GEMM kernels are used in BLAS libraries such as rocBLAS. For developers, the practical route is to use a compatible library or programming interface and confirm that its version supports the target GPU and required data types. AMD’s Matrix Core programming explanation
Do all AMD GPUs have the same Matrix Core capabilities?
No. Matrix Core support and performance characteristics vary across architectures and data types. AMD’s CDNA overview associates the technology with Instinct MI100, MI200, MI300, MI350, and MI400 families, but a feature available on one generation or model should not be assumed to apply to another. AMD CDNA architecture overview
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AMD’s current architecture page, for example, lists 1,024 Matrix Cores for the MI350 series and 1,216 for the MI325X. These are model-specific manufacturer specifications, not counts for every AMD GPU. The same page says MI350 TF32 support is software-emulated, illustrating why a listed format does not always mean native hardware execution. AMD CDNA architecture overview
Precision support is generation-specific
Data types matter because a GPU may support a format natively, support it through emulation, or not support it in the way a workload requires. AMD’s ROCm precision reference says CDNA3 natively supports FP8 FNUZ in E4M3 and E5M2 formats. AMD notes that this customized FP8 format differs from the FP8 format used with NVIDIA H100, so software and model compatibility should be checked rather than inferred from the label “FP8.” AMD ROCm precision support reference
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When checking compatibility, verify the exact accelerator, architecture generation, input and accumulation data types, and whether the required operation is native or emulated. Also check that the relevant library supports the intended workload and GPU.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What to compare when evaluating matrix workloads
For a meaningful comparison between AMD GPUs, check the details that determine whether the hardware and software can perform the same work:
- Exact model and architecture: Do not generalize a Matrix Core count or feature from one Instinct product to another.
- Data types: Match the required input and accumulation precision, and distinguish native support from emulation.
- Operation and mode: Check for support relevant to the workload, including any required sparse or microscaling modes.
- Software path: Confirm that the intended ROCm version and library support the target GPU and operation.
- Benchmark conditions: Compare results only when workloads, precision, and measurement methods match.
AMD’s documentation establishes generation-dependent capabilities, not a universal speedup figure. A Matrix Core count alone cannot predict the performance of a particular application.
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