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Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Repair Windows errors before they cause bigger problemsFix Now →Agentic AI chip design uses AI agents to coordinate tasks through electronic design automation (EDA) tools, interpret the tools’ results and iterate on a design. TSMC’s partners are building these workflows to help engineers manage increasingly complex chip, verification and packaging work—not because current announcements prove that AI can independently deliver a manufacturable chip.
What is agentic AI chip design?
Electronic design automation, or EDA, is the software engineers use to design, simulate, verify and prepare chips for manufacturing. In an agentic workflow, an AI system can plan or coordinate parts of that work, call EDA tools, examine their outputs and decide what to try next. The tools still perform the underlying design and analysis operations; the agent helps manage a sequence of them.
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That is different from asking a general-purpose chatbot to write a block of code. A chip design has to satisfy interacting requirements for function, timing, power, physical layout and manufacturability. A plausible-looking answer is not enough: the design must pass the relevant checks using the appropriate tools and constraints.
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How can AI agents help design and verify chips?
An agent can work across a feedback loop rather than produce a single answer. In a typical workflow, the loop might look like this:
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- Set up a task. An engineer or workflow defines the design goal, constraints and stage to address.
- Plan tool actions. The agent selects or coordinates work that can be carried out by available EDA tools.
- Run and inspect. It calls those tools and interprets outputs such as errors, test results or analysis reports.
- Revise and repeat. It can make or propose changes and run further checks, with engineers reviewing the design and deciding what to accept.
The stages can span architecture, register-transfer-level (RTL) design, synthesis and physical design. On the verification side, announced capabilities include generating design or testbench code, creating test plans and helping debug failures. These are examples of work an agent may assist with, not a guarantee that it can verify every property or certify a chip on its own.
Why are TSMC and its partners building these workflows?
Modern AI and high-performance-computing systems put pressure on chip performance and power efficiency while increasing the complexity of designs, advanced packaging and multi-die integration. TSMC contributes its process technologies, packaging platforms and design ecosystem; EDA companies contribute design software, optimization, verification capabilities and intellectual property. Coordinating tools with a foundry’s process and packaging requirements can help customers implement and check designs for a particular technology.
TSMC describes its EDA Tool Certification Program as support for customers using its technologies. Its listed partners include Cadence, Siemens EDA and Synopsys, with tool categories covering physical implementation, timing and power signoff, physical verification, extraction, simulation and thermal analysis. Certification is specific to the listed tool and technology combinations: TSMC’s certification table is dated July 10, 2026, so a particular combination’s status should be checked against the current listing.
Agentic workflows build on that existing EDA-and-foundry collaboration; chip-design automation did not begin with the latest AI announcements. For example, Synopsys and TSMC described certified digital and analog flows, multi-die design and packaging enablement, and customer tape-outs in a 2025 collaboration announcement. Enablement and supported process details can change over time.
What have the companies announced?
The announcements describe different roles and scopes. In particular, a company appearing in NVIDIA’s broader industrial-agent ecosystem is not thereby established as having the same role in TSMC’s EDA certification program.
| Company or collaboration | Announced focus | Tools, foundry or status established in the announcement |
|---|---|---|
| Cadence | ChipStack coordinates virtual engineers for semiconductor design and verification; NVIDIA’s announcement describes coding for designs and testbenches, test-plan creation and debugging. | Cadence says ChipStack uses Cadence EDA tools. Cadence separately reported that its established AI optimization and AI assistant solutions—not the newer ChipStack agent—had been used in over 1,000 tapeouts. |
| Synopsys and TSMC | Agentic workflows for analog, digital and multi-die design; one cited example is chiplet floorplan co-optimization. | The example uses Synopsys 3DIC Compiler and supports TSMC 3DFabric. The companies also announced a longer-running design and packaging enablement collaboration in 2025. |
| Siemens EDA | Named by TSMC as an EDA Tool Certification Program partner. | The certification program covers multiple EDA categories. The announcement evidence described here does not establish that Siemens has the same agentic workflow or role as the Cadence and Synopsys announcements. |
| NVIDIA’s broader industrial ecosystem | NVIDIA names Cadence, Dassault Systèmes, Siemens and Synopsys among companies bringing agentic AI into industrial platforms, including semiconductor and system workflows. | This is broader ecosystem context, not evidence that every named company participates in the same TSMC-specific EDA alliance. |
| Synopsys and OpenAI | A multi-year collaboration to develop a model optimized to use Synopsys EDA tools in semiconductor-design workflows. | The announcement describes a development direction—learning to run tools, interpret results and iterate—not proof that the planned product is generally available. |
Vendor statements describe intended benefits such as faster design, greater productivity and improved performance, power and area (PPA). Those aims should not be read as independently measured results for every workflow. An announcement that a toolchain is enabled does not establish a universal reduction in design time or a PPA gain across designs.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What still needs engineering review?
Agentic behavior does not remove the need to establish that a design is correct and suitable for its intended manufacturing process. Engineers still need to set constraints, assess whether tool outputs are valid, review proposed changes and complete the required verification and signoff. The more the workflow crosses design stages or integrates multiple dies, the more important it is to preserve context and check that a change in one area has not broken another.
Do these 3 things before closing this tab:
1Scan for outdated or missing drivers - takes under a minute2Repair Windows errors before they cause bigger problems3Fix the driver behind crashes, sound loss and screen glitches- Functional correctness: Does the design do what the specification requires?
- Timing and power: Does it meet the relevant targets under the specified conditions?
- Physical implementation: Does the layout respect physical constraints and integration requirements?
- Verification and signoff: Have the required checks been run and their results reviewed for the applicable process and design?
A 2024 research framework called AiEDA proposed an agentic open-source ASIC flow from concept toward GDSII and described a keyword-spotting ASIC case study. It is useful as research context for tool coordination across hardware-design stages, but it is not independent validation of the newer commercial offerings.
What can the announcements establish—and what can’t they?
The announcements establish that vendors and TSMC are enabling or developing agentic workflows around professional EDA tools, verification and advanced packaging. They also identify specific examples, such as Cadence’s front-end design and verification focus and Synopsys’s TSMC-supported chiplet floorplan co-optimization example.
They do not, by themselves, establish that one vendor’s approach is more accurate or productive than another’s, that every announced capability is generally available, or that an AI agent can take a design from specification to manufacturable chip without engineers. No independent comparative evaluation of the named agentic offerings is established by these announcements. Treat productivity and PPA claims as company-stated aims unless a particular workflow has been independently measured.
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