A complementary field-effect transistor (CFET) is a CMOS architecture that stacks an n-type transistor and a p-type transistor vertically in the same device footprint. Conventional CMOS pairs place those complementary transistors side by side. Stacking them is intended to reduce the lateral area needed for logic, but it does not change the underlying logic function.
What “complementary” and “stacked” mean
“Complementary” describes the two different transistor types used together in CMOS: an n-channel device (nMOS or nFET) and a p-channel device (pMOS or pFET). In a CFET, those remain distinct transistors, but one is positioned above the other rather than beside it. The vertical arrangement is the defining feature; channel shape, gate layout, contacts, and manufacturing sequence can vary among designs.
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A CFET is therefore a device architecture for implementing CMOS logic, not a new logic gate or a complete processor technology. Its main appeal is geometric: reducing the space consumed by the n- and p-type devices side by side could allow a smaller standard-cell footprint and denser layouts.
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| Feature | Conventional complementary pair | CFET |
|---|---|---|
| Placement | n-type and p-type transistors sit beside each other. | n-type and p-type transistors are stacked vertically. |
| Logic role | Implements complementary CMOS logic. | Also implements complementary CMOS logic; the architecture changes placement, not the basic logic function. |
| Area motivation | Lateral spacing between devices contributes to cell layout. | Vertical stacking is intended to reduce lateral footprint and support denser standard cells. |
| Implementation details | Depends on the chosen transistor and process technology. | Depends on channel geometry, gates, contacts, routing, and integration process. |
The potential area advantage is not the same as a guaranteed improvement in a finished chip. Cell layouts must still accommodate connections, power delivery, and routing.
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Why semiconductor researchers are studying CFETs
As transistor dimensions and standard-cell layouts are scaled, fitting complementary devices and their connections into less lateral space becomes increasingly difficult. Stacking offers a way to use vertical space instead. Imec has described CFET as a candidate for logic scaling beyond 1 nm, a roadmap direction rather than evidence that CFET is already a standard commercial process (imec, 2022).
Imec’s 2018 announcement described a proposed process flow with potential for 50% area scaling in standard cells and SRAM cells. That figure was a projection for that proposal, not a general measured result for CFETs (imec, 2018).
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A separate 2021 IEEE study modeled a particular CFET-versus-nanosheet-CMOS inverter comparison using 3-nm technology computer-aided design (TCAD). It reported an approximately 55% area reduction for the modeled case, alongside frequency and power differences under the study’s comparison assumptions. These are simulation results for one design point, not product benchmarks or universal CFET characteristics (IEEE Journal of the Electron Devices Society, 2021).
How CFETs could be manufactured
Two broad integration approaches are discussed in CFET development. They differ in how the stacked transistor tiers are made and brought together.
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Monolithic integration
In monolithic integration, the device tiers are built in a shared sequence on the same wafer. This can integrate the stack directly, but it creates demanding process-integration problems, including fabrication of high-aspect-ratio structures, patterning, and formation of source/drain contacts. Imec has described work toward a monolithic CFET process flow (imec, 2023).
Sequential integration
In sequential integration, one device tier is made separately and then transferred or bonded above another tier. This is a distinct route from building both tiers in a shared sequence; each approach brings its own integration constraints. The choice of route does not, by itself, establish a particular performance or area benefit.
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What has been demonstrated—and what remains unsettled
In 2024, imec reported electrically functional monolithic CMOS CFET devices with stacked bottom and top source/drain contacts. In the same work, forming bottom contacts from the wafer backside was presented as a feasibility result. For that research process, imec reported that the backside-contact approach improved the top-device survival rate from 11% to 79%; those percentages describe the reported fabrication result, not a general yield expectation (imec, 2024).
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A functional research device is an important demonstration, but it does not show that CFETs are broadly deployed in commercial processors or memory. The cited evidence establishes laboratory progress, not volume manufacturing, product availability, or a universal advantage over other transistor architectures.
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What to check when evaluating a CFET claim
Reported benefits depend on what is being compared and how the device is built. When reading about a claimed CFET improvement, check:
- Evidence type: Is the result a projection, a computer simulation, or a fabricated-device demonstration?
- Comparison: Which specific alternative, such as a nanosheet CMOS design, is used as the baseline?
- Architecture: What channel geometry, gate arrangement, and contact placement does the proposal use?
- Integration route: Are the tiers built monolithically or joined through sequential integration?
- Design consequences: Does the reported area account for cell routing and interconnect constraints? IEEE design research identifies routing as a challenge for compact stacked structures (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021).
These distinctions matter because a smaller modeled inverter, a projected standard-cell scaling opportunity, and an electrically functional device are different kinds of evidence. None alone establishes the performance, reliability, or manufacturability of a commercial chip.
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