A 130 nm process node is a name for a semiconductor manufacturing generation, not a guarantee that every transistor or chip feature measures exactly 130 nm. In Intel’s 2000 example, the company’s 130 nm process had a 70 nm transistor gate. The number is useful as historical shorthand, but the exact device dimensions and capabilities depend on the specific process.
What “130 nm” means
A nanometer (nm) is one billionth of a meter. In chip manufacturing, a process node identifies a generation of fabrication technology and its associated design and manufacturing capabilities. Historically, node labels followed physical scaling measures more closely than many present-day leading-edge labels, but “130 nm” did not mean that every layer or transistor dimension was 130 nm.
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The International Technology Roadmap for Semiconductors (ITRS) used DRAM interconnect half-pitch as a representative feature in its 2003 discussion of node scaling. Earlier node labels had coincided with measurements such as gate length and pitch; over time, the reference measure shifted. A Joint Research Centre report notes that below 28 nm, node names no longer correspond to a specific feature size or a meaningful, measurable wafer transistor-density quantity. These historical naming changes are why a node label should not be treated as a complete chip specification.
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There was no single set of dimensions shared by every 130 nm process. Intel’s November 2000 announcement provides one concrete, vendor-specific example: its 130 nm logic process used a 70 nm transistor gate and a 1.5 nm gate oxide. Intel also described copper interconnects, low-k dielectric, six layers of dual-damascene copper, and operation at 1.3 volts or less. Those figures describe Intel’s implementation, not universal requirements for a 130 nm process.
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So, a question such as “How big is a 130 nm transistor?” has no single answer from the node name alone. A transistor has multiple dimensions, and a process contains many different features and layers. To know the dimensions for a particular chip, look for specifications about that chip’s process and device structures rather than infer them from “130 nm.”
When did the 130 nm generation arrive?
The date depends on which milestone is meant. Intel announced that it had completed development of its 0.13-micron (130 nm) logic technology on November 7, 2000, and expected volume manufacturing to begin in 2001. The 2003 ITRS executive summary distinguishes that kind of target from production timing: the 2001 roadmap anticipated a 130 nm DRAM ramp in 2001, while manufacturer data showed the actual qualified production ramp in 2002. Development completion, a roadmap forecast, and a production ramp are different events.
Why do foundry offerings differ at the same node?
A node label does not tell you the full menu of devices, design rules, or process options a foundry offers. In a 2003 discussion, TSMC noted that device characteristics at 130 nm and 90 nm were no longer a straightforward extension of earlier generations, and highlighted trade-offs for mixed-signal designs. The practical choice is therefore about the specific process offering and the design’s needs, not just the number in the node name.
When comparing process options, check the foundry’s documented details for:
- Available transistor and device variants, including options suited to analog or mixed-signal circuits.
- Operating-voltage and power requirements.
- Performance and integration-density needs.
- Interconnect choices and manufacturing qualification.
- Cost for the intended design and production volume.
Why are 130 nm and other mature processes still used?
Smaller geometries are not automatically better for every chip. Texas Instruments wrote in 2024 that analog and embedded semiconductors in the 45 nm to 130 nm range remain ubiquitous. TI executives explained that many components in automobiles, industrial equipment, computers, and phone circuit boards do not need the smallest geometries. For some analog and RF designs, shrinking transistor geometries can increase cost without improving performance for the intended use.
That does not mean every 130 nm process is cheaper or better suited to every design. It means process selection depends on the circuit’s requirements: a mature process can be a sensible fit when its device options and characteristics meet those needs, while a denser or newer process may be preferable when the design benefits from its capabilities.
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What to remember
- “130 nm” names a manufacturing generation; it does not specify the size of every transistor or feature.
- Intel’s 70 nm gate and 1.5 nm gate oxide are details of its own 130 nm process, not universal node specifications.
- Foundry offerings at the same node can differ, so compare documented process capabilities against the design’s requirements.
- Mature processes remain useful when their characteristics suit the application; the smallest node is not automatically the right choice.
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