The Tool Desk
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What does transistor feature size mean?
The phrase is useful as shorthand, but it is ambiguous unless the speaker specifies what is being measured. A transistor has multiple physical dimensions, while a chip’s manufacturing process also includes structures beyond the transistor. A node name describes a process generation, not one universal length.
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Gate length
Gate length is a physical dimension of a transistor’s gate. The distinction between a node label and a measured feature is clear in a historical example: Intel announced in 2002 that its “90 nm” process would use transistors with a 50 nm gate length. That figure describes Intel’s process at that time, not a present-day convention or a conversion rule for other node names. Intel’s August 13, 2002 announcement made the claim.
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Pitch is the repeat spacing between features in a layout. It is a spacing measurement, not the same thing as gate length. Semiconductor roadmaps distinguish attributes such as contacted gate pitch and the pitch of the tightest metal layer, so a statement about “pitch” should identify which features it concerns. The 2022 International Roadmap for Devices and Systems (IRDS) executive summary treats these as separate attributes.
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Process node and node label
A process node refers to a manufacturing technology generation: a fabrication recipe and the component architecture used to build transistors and interconnects. Intel describes a node as involving thousands of steps and says node characteristics include transistor size and density, power efficiency, performance, cost, thermal management, and other features. Its explanation also notes that modern names are closer to representations of density and/or performance than the older physical-measurement naming. See Intel’s process-node explainer.
That does not mean node names have no relationship to process capability. It means a label such as “4 nm” does not, by itself, tell you that the transistors have a 4 nm gate length—or give you a complete, directly comparable description of the process.
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Why node names stopped being literal measurements
Historically, technology-node naming was tied more closely to physical scaling. The IRDS history describes the original node convention in terms of the half-pitch of the tightest metal layer in an integrated circuit. Through the 1970s, 1980s, and much of the 1990s, gate length and metal half-pitch were roughly similar, so one figure could serve as a useful shorthand for both density-related scaling and a performance relationship. The IRDS 2021 executive summary and IRDS 2022 executive summary describe this history.
As gate dimensions and metal pitch scaled differently, the connection between a node label and a single physical feature weakened. The IRDS account describes naming approaches that moved from averaging metal half-pitch and gate length, to using gate dimensions, and later to defining successive labels as a percentage of the preceding label. Over time, the label became detached from a direct measurement of a particular feature.
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Intel’s 2021 naming announcement says that “traditional nanometer-based process node naming stopped matching the actual gate-length metric in 1997.” That date is Intel’s characterization in its announcement, not a universal industry standard or an independently established cutoff. Intel’s 2021 announcement also described its naming framework as intended to give customers a more accurate view of process nodes.
Why transistor architecture matters
Physical dimensions do not tell the whole story because the transistor’s structure affects how it operates and scales. TSMC says its processes used planar transistor structures until FinFETs entered production with its 16 nm technology in 2014. The company describes FinFETs as addressing poor electrostatic channel control at short gate lengths and allowing density scaling to be partly decoupled from effective device-width scaling. This is one reason a single size figure cannot capture a process’s structure or capability. See TSMC Research’s overview of logic technology.
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How to compare process generations
Do not infer that chips with the same node number use the same physical dimensions, or that a smaller-sounding label guarantees a particular advantage. For a meaningful comparison, identify the metric and look for published, comparable data. Useful measures include:
- Contacted gate pitch: spacing associated with contacted gates.
- Metal pitch: the repeat spacing of a specified metal layer, ideally the same layer or comparable layer in both processes.
- Gate length: a physical transistor dimension, when the manufacturer publishes it.
- Cell area or transistor density: measures related to how much logic can fit in a given area; check how each source defines and measures them.
- Power, performance, and area (PPA): practical process-evaluation measures that help explain what a design can achieve, rather than what its node name implies.
Intel identifies PPA as primary process-evaluation metrics, while the IRDS roadmap separately tracks gate and metal pitches. Comparing a named physical metric alongside PPA is more informative than comparing node labels alone. The available sources do not establish a neutral, current cross-vendor table of transistor dimensions, so a node number should not be used to invent one.
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