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System Management Mode (SMM) is a special processor mode reserved for system firmware. On Intel processors, a system management interrupt (SMI) switches the CPU into SMM, where firmware runs an SMI handler using System Management RAM (SMRAM). When the handler finishes, it executes RSM to restore the interrupted state and resume normal execution.
What SMM means—and what it does
SMM is an architectural operating mode for system-wide firmware tasks, such as power management, hardware control, and proprietary OEM functions. It is not an operating-system service, and ordinary applications do not run in it. Intel describes the mode in its Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C.
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Four terms describe the basic mechanism:
- SMM: the processor mode in which system firmware handles the task.
- SMI: the system management interrupt that triggers entry into SMM.
- SMRAM: memory used for the SMI handler’s code and data, including saved processor state.
- RSM: the instruction the handler uses to leave SMM and resume the interrupted program.
How an SMI moves the processor into SMM
- An SMI arrives. On Intel architecture, an SMI is a nonmaskable external interrupt that operates outside the ordinary interrupt and exception mechanisms.
- The processor reaches a safe transition point. Intel’s architecture documentation says the processor completes instruction retirement and outstanding stores before entering the handler.
- Processor state is saved. The processor saves the interrupted context in SMRAM and begins executing the firmware’s SMI handler in the SMM environment.
- The handler performs its work. The specific work depends on the system firmware and the platform.
RSMrestores execution. The handler executesRSM, which restores the saved processor state and transfers control back to the interrupted program. Intel identifiesRSMas the architectural way to exit SMM.
Intel describes SMM as non-reentrant: the processor does not service nested SMIs while it is already in SMM. These details describe Intel IA-32 and Intel 64 processors, not a universal specification for every processor architecture.
What happens inside the SMM environment
On Intel processors, the initial SMM environment has paging disabled and starts in real-address mode. In that initial environment, the handler can address up to 4 GiB; it may switch modes while remaining in SMM. These are architectural details, not a statement about the memory size of a particular computer. See Intel’s Volume 3C system programming manual.
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How SMM relates to SMRAM security
Saving processor state and running a handler in a separate environment make SMM distinct from ordinary execution. Intel’s security guidance describes SMRAM as holding critical SMI-handler code and data, and says systems typically use sequestered DRAM isolated from host DRAM. The actual memory protection and firmware configuration are platform-specific; the architectural definition alone does not establish how a particular computer is configured.
SMM’s separation should not be mistaken for proof that firmware is secure. The handler is privileged, security-sensitive firmware, and its protections depend on the system implementation. Intel discusses SMM and SMRAM in its host firmware speculative execution side-channel mitigation guidance.
How SMM is handled with Intel virtualization
Intel documents two approaches to SMI handling in systems using VMX virtualization. The default approach has system firmware handle the SMI and then resume VMX operation. An optional dual-monitor approach uses an executive monitor outside SMM and an SMM-transfer monitor inside it. Dual-monitor support depends on the processor and is not available on every Intel processor.
Where to find the architectural definition
For the precise Intel-specific description, consult Chapter 32 of the Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C. Intel’s manuals page, updated September 21, 2026, lists the current manuals: Manuals for Intel 64 and IA-32 Architectures.
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