SoC PLANNER is a pre-synthesis design flow for exploring system-on-chip architectures, comparing their power, performance and area trade-offs, and generating RTL for selected configurations. CEA, Defacto Technologies and Innova Advanced Technologies announced on September 8, 2026, that the three-year collaborative project was ready for early adopters. Their announcement also reports exploration cycles up to 30–40% shorter in the project’s industrial use cases; that is a partner-reported result, not an independently established performance guarantee.
What SoC PLANNER does
SoC PLANNER connects several early stages of chip development: architecture specification, design-space exploration, design-flow coordination and RTL generation. It is a planning and design software flow, not a finished chip or a claim that every stage of semiconductor production is automated.
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Its purpose is to help engineering teams examine architectural alternatives before synthesis. A team defines parameters and ranges to explore, identifies target measures and priorities, then evaluates candidate configurations. The flow estimates area, performance—including bandwidth and latency—and power, identifies Pareto-optimal options, assigns eco-design footprint scores, and can generate RTL for configurations the team selects.
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How the components fit together
The project announcement assigns separate roles to three technologies. Together, they are presented as a flow from defining and exploring architecture options to coordinating the work and generating RTL.
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- CEA’s A-DECA: performs multi-objective design-space exploration using simulation, analytical models and AI-assisted optimization.
- Defacto Technologies’ SoC Compiler: transforms selected architecture configurations into synthesizable RTL.
- Innova Advanced Technologies’ PDM: coordinates design flows, computing resources and engineering data.
In practical terms, exploration narrows a broad configuration space to candidate designs; orchestration manages the associated engineering flow; RTL generation turns selected choices into a design representation that can proceed to downstream work. The announcement describes the RTL as implementation-ready, but does not publish the datasets, detailed configurations or evaluation protocol needed to independently assess that characterization.
How the trade-offs and sustainability score work
Comparing architecture objectives
Power, performance and area are competing objectives rather than a single score that always improves in one direction. For example, a configuration that reduces latency may require more power or silicon area. Teams can set target KPIs and priorities—such as emphasizing power, performance or area efficiency—and use the estimates to compare options.
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A Pareto-optimal configuration is one where improving one objective would require accepting a worse result in at least one other objective. Pareto analysis therefore helps expose meaningful trade-offs instead of implying that one design is best on every measure. The project announcement describes the platform as identifying these configurations; it does not supply an independent assessment of the optimizer’s accuracy.
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Adding eco-design to the decision
SoC PLANNER’s announced approach adds an eco-design footprint score alongside conventional power, performance and area considerations. This makes sustainability a criterion teams can weigh during architecture exploration, rather than a topic considered only after a configuration has been chosen.
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The announcement does not define the score’s calculation, boundaries or underlying environmental data. It therefore supports saying that an eco-design score is included in the workflow, but not claiming that the platform measures a particular lifecycle impact or provides a standardized environmental assessment.
What the project scenarios and speed claim show
The partners describe two validation scenarios: a configurable AI accelerator with trade-offs involving latency, power, energy use and silicon area, and an HPC processor based on the Rhea platform. For the Rhea-based scenario, the announcement says thousands of architectural alternatives were evaluated.
Across the industrial use cases, the partners report up to 30–40% shorter exploration cycles. This is the project announcement’s reported result. It does not provide a full benchmark protocol, baseline configurations, uncertainty ranges or third-party replication, so the figure should not be treated as a universal saving or an independently verified benchmark. The announcement also does not establish that the same reduction would apply to a different design team, workload or process.
What early-adopter readiness means
The project partners’ September 8, 2026 announcement says, “SoC PLANNER is now ready for early-adopters.” CEA-List’s official news listing records the announcement on the same date. These announcements establish the project’s stated early-adopter readiness, not a general commercial release.
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The available announcement does not establish pricing, licensing terms, a public signup path or a procurement route. It also says the work was funded by BPI France as part of the France 2030 program. No head-to-head comparison with competing platforms is established by these announcements.
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