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On NVIDIA’s SM120 target, a dependent machine-code instruction can safely use a producer’s register result only when the hardware schedule gives that result enough time to become available. A community reverse-engineering project reports that SM120 relies on scheduling metadata for fixed-latency dependencies; if the encoded delay is too short, a consumer may read stale register contents without a fault or warning. This is a community finding, not an NVIDIA-published guarantee, and the reported measurements came from one GeForce RTX 5070 Ti.
What “result visibility” means for an instruction dependency
Here, result visibility means that a producer instruction has made its register result available for a dependent instruction in the same thread to consume. It is a question about instruction timing and machine-code scheduling: if the consumer is issued too soon, it may use the register’s earlier contents rather than the producer’s new result.
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This is different from visibility in PTX’s formal memory model. In the PTX ISA, communication order describes visibility among overlapping memory operations. That relation concerns memory effects; it is not a synonym for a register result becoming ready for a same-thread instruction dependency. NVIDIA’s PTX ISA reference, version 9.4, describes PTX as a virtual ISA whose programs are translated to the target hardware instruction set.
What the SM120 report says can happen
The community project basalt reports that fixed-latency instruction dependencies on SM120 rely on scheduling metadata encoded in machine instructions. According to the project, if the scheduled delay is not long enough, a dependent instruction can read stale register contents. The report says this can happen without a fault or warning.
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That describes a machine-code scheduling risk, not a PTX language rule or an official NVIDIA specification. A PTX program expresses operations at a virtual-ISA level; the target-specific machine instructions and their scheduling metadata are a lower-level implementation. A claim about an encoded delay on SM120 should therefore not be presented as a general promise about PTX behavior.
What has been measured—and how far it applies
The available findings are community characterizations, with distinct scopes. They should be read as observations from particular work, not as guaranteed values for every GPU.
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| Evidence | Reported finding | Scope and status |
|---|---|---|
| SM_120 Microarch Reference | fma.rn.f32 is listed as mapping to FFMA, with a measured four-cycle latency. |
Community measurement; not an official NVIDIA latency guarantee. The listed fact does not establish that every producer-consumer sequence has the same effective timing. |
| basalt | Fixed-latency dependencies on SM120 rely on scheduling metadata; an insufficient delay can allow a stale register read. | Community reverse-engineering finding, not an NVIDIA-published specification. The project author reports measurements on one GeForce RTX 5070 Ti. |
| NVIDIA PTX ISA references | PTX is a virtual ISA translated to target hardware. PTX ISA 8.7 added support for sm_120 and sm_120a. |
Official documentation establishes the PTX framing and target support; it does not establish the community’s specific SM120 scheduling claim. |
The project author explicitly cautions that SM120 measurements should not be carried over to SM100 merely because both architectures are Blackwell. The reported single-card scope also does not establish that every SM120 GPU behaves identically. For another architecture or card, the relevant dependency and machine code need their own evidence.
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Use PTX to understand the program’s virtual-ISA operations
PTX is useful for seeing what operations the compiler is asked to translate and for understanding the program at the documented virtual-ISA level. NVIDIA’s PTX ISA 8.7 is the cited point at which support for sm_120 and sm_120a was added; the current reference identified here is PTX ISA 9.4. Neither fact makes PTX a record of every target-specific scheduling choice.
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Inspect generated machine code for a scheduling claim
If the question is whether an SM120 consumer is scheduled late enough to use a producer’s register result, inspect the generated target machine instructions and their scheduling metadata. Record the target, the actual producer-consumer pair, and the encoded delay. A PTX listing alone cannot establish what lower-level schedule was emitted.
Measure hardware to test behavior on a specific target
A hardware experiment can check a machine-code hypothesis on the GPU tested. To make the result interpretable, identify the GPU model and target architecture, the instruction and dependency under test, the latency assumed or measured, and whether the evidence comes from compiled PTX or inspected machine code. Keep the conclusion scoped to those conditions: the cited basalt work reports one RTX 5070 Ti, not a survey of all SM120 products.
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Conceptual understanding does not require buying a GPU. Reproducing the cited measurements does require access to an SM120 GPU and suitable low-level tooling; the RTX 5070 Ti is the card the project author says was used, not a universal requirement or recommendation.
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