A segmented address space divides memory into variable-sized logical regions, such as code, data, or a stack. A program’s logical address identifies a segment and an offset within it; system metadata uses that pair to locate the requested address and can enforce bounds and access permissions.
What is a segmented address space?
It is a memory model in which an address space is organized into distinct segments rather than treated only as one continuous range. Segments correspond to logical units of a program and can differ in size. A segment might contain code, data, a procedure, an array, or a stack.
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The general model describes a logical address as two parts: a segment identifier and an offset within that segment. The segment identifier selects the relevant region; the offset specifies a location relative to its beginning.
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How do a segment and offset form an address?
- Select the segment. The segment number or selector identifies a segment-table entry or descriptor.
- Read its metadata. The entry supplies information such as the segment’s base address, limit, and access rights.
- Check the offset. The system verifies that the requested offset falls within the segment and that the access is permitted.
- Form the address. If the checks pass, the base and offset are used to form the next address in the translation process. An invalid segment or out-of-range offset can cause a fault or trap.
This is the general idea; the precise format and translation stages depend on the architecture. In IA-32 protected mode, for example, a logical address consists of a 16-bit segment selector and a 32-bit offset. The selector identifies a descriptor in the Global Descriptor Table (GDT) or Local Descriptor Table (LDT). The descriptor contains the segment base, limit, and access information. After checking access and range, the processor adds the offset to the base to produce a linear address. If paging is enabled, paging then translates that linear address to a physical address. Intel’s IA-32 architecture manual describes this architecture-specific process.
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What are the benefits and trade-offs?
- Logical organization: Segments can reflect meaningful program units instead of requiring every region to be treated as part of one undifferentiated range.
- Bounds and permissions: Segment metadata can limit access to a region and give different segments different permissions.
- Sharing: Processes can map shared segments to common memory, where the system’s mappings and permissions allow it.
- External fragmentation: Because segments have variable sizes, allocating them in physical memory can leave gaps too small or poorly placed for later allocations.
- Translation overhead: The system must maintain segment metadata and validate addresses. Combining segmentation with paging adds a further translation stage and additional tables.
How is segmentation different from paging?
Segmentation organizes an address space into variable-sized logical regions. Paging divides memory into fixed-sized pages. The distinction is about both how the address space is represented and how memory is allocated: a segment can match a program unit and have its own limit, while pages are uniform-sized units.
| Aspect | Segmentation | Paging |
|---|---|---|
| Address-space organization | Logical regions such as code, data, or stack | Fixed-sized pages |
| Allocation unit | Variable-sized segment | Fixed-sized page |
| Bounds and permissions | Can be associated with each segment | Managed through page-level translation and permissions, depending on the system |
| Fragmentation trade-off | Variable-sized physical allocation can cause external fragmentation | Fixed-sized allocation avoids external fragmentation in the sense of gaps between variable-sized allocations |
| Translation | Segment metadata maps the segment and offset | Page tables map pages and offsets |
Some systems combine the approaches: segmentation provides logical regions, and paging manages physical memory in fixed-sized units. That combination also means address translation involves both mechanisms.
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What does a flat address space mean in IA-32?
Segmentation’s general model should not be mistaken for the way every processor exposes memory to software. In IA-32 protected mode, a flat model can make segmentation largely invisible: code and data descriptors can cover the same linear address range. Segmentation remains part of the architecture’s translation and protection machinery, but programs can operate as though they see a continuous range.
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The 16-bit selector and 32-bit offset described above are specific to IA-32 protected mode, not a universal segmented-address format. Likewise, the IA-32 manual’s description of segments as large as 232 bytes (4 gigabytes) belongs to its 80386 model; it is not a general limit for all segmented address spaces.
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Keep the address stages distinct
In architectures that use these stages, a logical address is the segment-and-offset input; segmentation can produce a linear address; and paging, when enabled, can translate the linear address to a physical one. These terms describe different points in the process, not interchangeable names for the same address.
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