Rowhammer is a disturbance effect in DRAM: repeatedly activating certain memory rows can alter data in nearby rows, even when software never directly accesses those neighboring cells. A resulting bit flip may corrupt data; it becomes a security exploit only if an attacker can make a useful change and exploit it. DDR4 and DDR5 research has demonstrated flips on specific tested systems, but that does not establish that every system using those memory generations is vulnerable.
How can accessing one part of RAM affect another?
Dynamic random-access memory (DRAM) stores data in cells arranged in rows. The row a process repeatedly activates is an aggressor; a nearby row whose stored data is disturbed is a victim. Under susceptible conditions, repeated high-rate activation can disturb the electrical charge in neighboring cells. If the disturbance is not corrected before it accumulates, a stored 0 may become 1, or a 1 may become 0.
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The important detail is that the affected cell need not be the one the process accessed. The simplified chain is: repeated activation of aggressor row or rows → disturbance in a neighboring victim row → possible bit flip → possible data corruption or security impact. Ordinary reads do not automatically flip bits: the outcome depends on activation intensity, the DRAM, refresh behavior, memory-controller behavior, configuration, and operating conditions. Intel describes Rowhammer as a DRAM reliability issue that can affect integrity, confidentiality, or availability if successfully exploited. Intel’s Rowhammer guidance explains the risk and layered protections.
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Repair Windows errors before they cause bigger problemsFix Now →Scan for outdated or missing drivers - takes under a minuteDriver Scan →Rowhammer is a physical memory disturbance effect, not a software bug limited to one operating system. Software can influence memory access patterns, and platform protections can affect whether those patterns cause damage, but the disturbance occurs in DRAM.
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When does a bit flip become a security exploit?
A bit flip is a change in stored data; by itself, it is not proof of a break-in. It becomes a security issue when an attacker can induce a change in data that matters—such as a page-table entry, key, or executable logic—and then use that change to gain an unintended capability. Success depends on the hardware, software, target data, and attack conditions.
In 2015, Google Project Zero described two working privilege-escalation exploits. In one, an unprivileged userland process induced flips in page-table entries on a tested x86-64 Linux system, then used an altered entry to gain read-write access to physical memory. This demonstrated an attack on the tested setup; it does not mean every machine can be compromised the same way. The Project Zero report documents the experiments.
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What have DDR4 and DDR5 tests shown?
Studies have demonstrated Rowhammer flips on selected systems using both DDR4 and DDR5. Their results establish that the effect is not confined to an obsolete memory generation; they do not measure the share of all computers or DIMMs that are vulnerable. Counts below describe each study’s tested sample and setup, not the prevalence of vulnerable memory in general.
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| Study and memory tested | Reported result | How to interpret it |
|---|---|---|
| ETH Zurich’s ZenHammer study, associated with USENIX Security 2024; tested AMD Zen platforms using DDR4 | Flips on 7 of 10 tested Zen 2 devices and 6 of 10 tested Zen 3 devices, despite deployed TRR mitigations | These are results from the study’s selected devices and methodology, not rates for all Zen systems or DDR4 memory. |
| ETH Zurich’s ZenHammer study; one tested DDR5 device among 10 devices | The study reports flips on a DDR5 device | A result from that tested sample does not establish that all DDR5 systems are vulnerable. |
| ETH Zurich’s Phoenix study; 15 SK Hynix DDR5 DIMMs manufactured between late 2021 and late 2024 | All 15 tested DIMMs were vulnerable to one of the two tested patterns; the page reports 4,989 average bit flips. It also reports that researchers reproduced a privilege-escalation exploit in an average of 5 minutes 19 seconds. | These results apply to the tested vendor, DIMMs, patterns, and study setup, not to the DDR5 market as a whole. The Phoenix research page reported these figures when accessed on 2026-10-07. |
A flip demonstration and an end-to-end exploit are different findings. The Phoenix page reports both for its study; the ZenHammer figures above describe observed flips. Do not infer an exploit against a particular computer from a memory-generation label alone.
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Does ECC RAM prevent Rowhammer?
No single ECC label guarantees immunity. Error-correcting code (ECC) is intended to detect or correct certain memory errors; it is a resilience layer, not necessarily a mechanism that prevents the underlying disturbance. The result depends on the ECC implementation and platform, among other factors.
Phoenix reports bit flips despite DDR5 on-die ECC. Separately, the USENIX Security 2025 presentation “ECC.fail: Mounting Rowhammer Attacks on DDR4 Servers with ECC Memory” describes an end-to-end attack on tested Intel servers using Hynix DDR4 ECC memory. The authors’ result shows that ECC does not categorically prevent every Rowhammer-related security outcome; it is not evidence that every server or ECC scheme can be attacked in the same way.
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What do the main mitigations do—and what can they miss?
Protections operate at different layers. Some aim to limit disturbance; others detect or correct residual errors, reduce an attacker’s ability to target memory, or help operators manage exposure. They are not interchangeable.
| Protection | Where it operates and what it does | Limit or trade-off |
|---|---|---|
| TRR-like DRAM protections and refresh management | DRAM-side mechanisms intended to manage repeated row activations or refresh behavior. | ZenHammer reported flips on selected DDR4 devices despite deployed TRR. Protection and effectiveness depend on the DRAM and implementation. |
| On-die ECC and system-level ECC | DRAM-side or platform-level error correction can help address some residual errors. | Neither should be treated as a guarantee that disturbance cannot happen or that every security-relevant outcome is prevented. |
| Memory-controller and platform protections, including pTRR | Controller and platform features can help limit exposure through supported mechanisms. | Availability depends on the platform, memory, and configuration; a feature name alone does not prove a particular system is protected against every pattern. |
| Higher refresh rates | Refreshing more often can reduce the time for disturbance to accumulate. | It can have performance or power costs and is not a universal fix. In Phoenix’s test systems, tripling refresh (tREFI approximately 1.3 microseconds) stopped that study’s patterns from triggering flips; the researchers measured 8.4% SPEC CPU2017 overhead for this mitigation in their evaluation. Those figures are test-specific, as reported on the Phoenix page accessed 2026-10-07. |
| Operating-system controls | Controls that make it harder for unprivileged users to identify physical memory adjacency may complicate some attacks. | Intel says this is not sufficient by itself; operating-system measures do not replace hardware and platform protections. |
| Firmware settings and operational controls | Supported firmware options, DRAM selection, workload isolation, monitoring, and response can contribute to a layered approach. | Settings and their effect vary by system. They require platform-specific guidance and validation. |
Intel’s guidance summarizes the layered approach: “No single mitigation completely eliminates Rowhammer risk; instead, protections aim to reduce the likelihood of disturbances and limit the impact of any residual errors.” Intel, “Reducing Exposure to Rowhammer.”
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What should you do on an installed computer?
- Identify the exact system and memory configuration. A DDR4 or DDR5 designation alone does not establish whether a particular computer is susceptible or which protections it supports.
- Ask the system or DRAM manufacturer about that platform. AMD’s response to ZenHammer recommends checking with the DRAM or system manufacturer about susceptibility. Its listed mitigations include ECC-supporting DRAM, refresh rates above 1x, disabling memory burst or postponed refresh, and supported Maximum Activate Count (MAC) capabilities; these depend on platform support and settings. See AMD bulletin AMD-SB-7021.
- Use only supported firmware and memory-controller settings. Confirm what a setting does for your model with its manufacturer rather than assuming a similarly named option has the same effect everywhere.
- For managed or higher-risk systems, consider operational controls as part of a wider plan. Workload isolation, monitoring, and response can complement technical protections; operating-system restrictions alone are not a complete defense.
Buying generic RAM, ECC memory, or a motherboard is not an evidence-backed universal fix. The available guidance points to protections and settings specific to the installed platform.
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