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What is Q.ANT’s Native Processing Unit?
Q.ANT announced its first commercial Native Processing Unit on November 19, 2024. The company describes it as a processor that uses light rather than electrons for selected computations, based on its LENA architecture—short for Light Empowered Native Arithmetics—and photonic integrated circuits made with thin-film lithium niobate. The accelerator connects to a host system over PCI Express.
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In plain terms, it is a specialized optical accelerator for certain mathematical operations, not a computer that performs every task with light. Q.ANT describes operations such as multiplication and Fourier transforms as suitable for implementation in the optical domain. The documented system still has conventional computing components to run the host operating system, software, and other parts of a workload.
How does a photonic NPU fit into a computer?
The documented deployment pairs the photonic card with a conventional x86 server. The server handles the surrounding computing and software environment; the NPU is intended to accelerate selected operations. That makes it a co-processor model, rather than a replacement for a CPU or GPU across an entire system.
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Q.ANT’s NPS 2 technical data sheet describes a 19-inch, 4U rack server with a system node based on x86 architecture and support for multiple NPU cards. The listed software environment includes Debian or Ubuntu Linux, a Linux device driver, C/C++ and Python APIs, and PyTorch integration marked “Pilot integration.” Those details describe the NPS 2 configuration in that 2025 data sheet, not necessarily every NPU generation or deployment.
What does the NPS 2 specification say?
The following figures are specifications in Q.ANT’s NPS 2 technical data sheet dated November 11, 2025. They should not be generalized to all photonic processors or later product configurations.
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| Item | NPS 2 specification |
|---|---|
| Server form factor | 19-inch, 4U rack server |
| Server dimensions | 178 mm high, 482 mm wide, 595 mm long |
| NPU card | Full-length, three-slot PCIe Gen4 x8 |
| System memory and I/O | Shared memory and I/O windows |
| Listed NPU throughput | 8 GOPS |
| Listed NPU power consumption | 150 W |
| Operating temperature | 15–35°C |
| Photonic core | Z-cut lithium niobate |
| Networking | Two 10 Gbit Ethernet interfaces and one 1 Gbit service interface; optional InfiniBand adapter |
| Software interfaces | Linux device driver; C/C++ and Python APIs; PyTorch integration marked “Pilot integration” |
What workloads is it meant to accelerate?
Q.ANT has identified AI inference, machine learning, image processing, and physics simulation as target or demonstrated workload areas. In a June 23, 2026 company release, it said it had demonstrated a diffusion model and an xLSTM recurrent time-series model on its second-generation NPU at ISC High Performance 2026. The same release said developers at Daisytuner compiled and deployed an object-detection model from PyTorch.
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How should Q.ANT’s performance claims be read?
Q.ANT has reported substantial efficiency and performance figures, but they are company claims with particular scopes—not independent, general-purpose benchmarks. Its November 2024 launch announcement claimed “at least 30 times greater energy efficiency” than traditional CMOS technology. Later NPS materials used “up to 30x” energy-efficiency and “50x” performance-gain-per-application framings. The June 2026 release tied its 30x framing to equivalent matrix operations at the photonic-circuit level.
A circuit-level comparison does not, by itself, establish lower energy use or higher performance for a complete application or server. The NPS 2 sheet’s listed 8 GOPS throughput and 150 W NPU power figure also cannot be directly compared with another processor without matching the workload, precision, measurement method, and power boundary.
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The 2024 announcement additionally described Q.ANT’s own tests and simulations. It reported 43% fewer parameters and 46% fewer operations for simulated Kolmogorov–Arnold Networks. For an image-recognition result, it reported 0.1 million parameters and 0.2 million operations, compared with 5.1 million parameters and 10 million operations for a conventional approach. These are company-reported results, not independently audited comparisons across general workloads.
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For a meaningful comparison with a CPU, GPU, or another accelerator, ask for results on the same workload and precision, including end-to-end latency and throughput, software and model-conversion requirements, total system power, and host-system configuration. A headline efficiency ratio is not enough to determine how a full deployment will perform.
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What has been announced about availability and use?
In its June 23, 2026 release, Q.ANT said IONOS placed the first commercial orders for the hardware in May 2026. The company also said Leibniz Supercomputing Centre and Jülich Supercomputing Centre were running its hardware in live production. These are milestones reported by Q.ANT; the release does not, on its own, provide independent deployment-performance results or establish broad availability.
Why does “NPU” need clarification?
In many computing contexts, NPU means “neural processing unit,” commonly referring to hardware for neural-network workloads. In this article, it means Q.ANT’s “Native Processing Unit,” a photonics-based accelerator. The shared abbreviation does not mean the architectures or capabilities are interchangeable.
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