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1Repair Windows errors before they cause bigger problems2Fix the driver behind crashes, sound loss and screen glitches3Clear out junk files and repair common Windows errorsNMOS and PMOS are the two channel polarities of MOSFETs: an enhancement-mode NMOS conducts when its gate is sufficiently positive relative to its source, while a PMOS conducts when its gate is sufficiently negative relative to its source. CMOS circuits combine both types for complementary switching.
What NMOS and PMOS mean
Both are metal-oxide-semiconductor field-effect transistors (MOSFETs). The letters describe the channel type and its majority carriers: an NMOS has an n-type channel in which electrons carry charge; a PMOS has a p-type channel in which holes carry charge. A gate’s electric field controls whether a conducting channel forms between the source and drain.
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In the introductory structure, an NMOS has n-type source and drain regions in a p-type body. A PMOS has p-type source and drain regions in an n-type body. Integrated CMOS processes provide the complementary body polarity using a well. Source and drain regions are often physically similar; the names describe their electrical roles in a circuit, not permanently different kinds of terminal. Harvey Mudd College’s CMOS VLSI Design chapter and MIT OpenCourseWare’s Computation Structures materials explain these device structures and roles.
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How their gate controls differ
For the standard enhancement-mode model, the important quantity is gate voltage relative to source voltage—not an absolute voltage called “high” or “low.” NMOS turns on when its gate-to-source voltage exceeds its threshold. PMOS turns on when the gate is sufficiently below its source: its source-to-gate voltage must exceed the magnitude of its threshold.
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| Feature | NMOS | PMOS |
|---|---|---|
| Channel and majority carrier | n-channel; electrons | p-channel; holes |
| Introductory source/drain doping | n-type | p-type |
| Introductory body doping | p-type | n-type |
| Enhancement-mode turn-on condition | VGS > VTN: gate sufficiently above source | VSG > |VTP|: gate sufficiently below source |
| Common digital schematic cue | Usually no gate bubble | A gate bubble commonly denotes inverted control polarity |
The bubble is a schematic convention; interpret the symbol and notation used in the circuit. Threshold values vary by device and fabrication process, so there is no universal voltage at which every NMOS or PMOS turns on. The gate conditions above describe enhancement-mode devices, not every MOSFET operating mode.
How they work together in CMOS
CMOS means complementary metal-oxide-semiconductor: it is a circuit technology that uses both nMOS and pMOS devices, not another name for either transistor individually. In a simple CMOS inverter, a low input turns on the PMOS, which supplies the output toward the positive rail. A high input turns on the NMOS, which pulls the output toward ground. This is the basic idea of complementary control; other CMOS circuits can have more complex arrangements. MIT’s course material introduces MOSFETs in this logic context.
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What the distinction does not tell you
- “High” and “low” are shorthand for gate voltage relative to source voltage and threshold; they are not universal absolute voltage levels.
- Electrons and holes identify the majority carriers associated with each channel type. Do not confuse their physical movement with the direction of conventional current.
- The channel polarity alone does not establish a universal speed, drive-strength, leakage, or sizing comparison. Those depend on the fabrication process and circuit design.
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