The right MOSFET depends first on what the circuit asks it to do: switch current, amplify a signal, or handle power. This first installment builds a practical specification, explains the datasheet numbers that matter, and shows how to estimate losses, temperature, gate-drive needs, and design margin before simulation and hardware testing.
Start with the MOSFET’s job
A MOSFET (metal-oxide-semiconductor field-effect transistor) uses an electric field at its gate to control a conductive channel between drain and source. The body is the fourth terminal. In many discrete power MOSFETs, the body structure also creates an intrinsic body diode that conducts in one direction when the transistor channel is off.
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The gate is insulated, so steady-state gate leakage is normally very small. It is not accurate to call the gate a zero-current input, however: charging and discharging gate capacitance requires transient current, and that current affects switching speed, driver size, ringing, and power consumption.
Device families
- N-channel and p-channel: N-channel devices generally offer lower resistance for a given die area; p-channel devices can simplify some high-side arrangements at lower performance.
- Enhancement mode: The usual power-switch type, normally off until sufficient gate-to-source voltage is applied.
- Depletion mode: Normally on at zero gate bias and used in specialized circuits.
- Discrete power MOSFETs and integrated MOS transistors: A power transistor’s large die, package, body diode, and thermal structure are not interchangeable with an integrated analog or CMOS device.
In some low-voltage structures, source and drain behavior is partly application-dependent, but package construction and the body diode still impose practical current and voltage limits.
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Choose the design branch
Do not begin by searching for a MOSFET with a convenient headline current rating. First identify the operating role.
| Role | Primary design questions | Key parameters |
|---|---|---|
| Switch | Can it block the worst-case voltage, transition cleanly, and dissipate the losses? | RDS(on), gate charge, Miller charge, capacitances, body-diode behavior, SOA |
| Analog amplifier | What bias point, gain, linearity, noise, and bandwidth are required? | gm, ro, bias stability, capacitances, distortion, noise |
| Power stage | How do voltage, current, heat, transients, and layout interact? | Voltage margin, RMS current, losses, package thermal data, transient behavior, layout |
| Integrated CMOS | How do process geometry and parasitics set circuit behavior? | Channel length, threshold, body effect, short-channel effects, process models |
This installment concentrates on the low-side switching and general power-design path, then provides a separate analog branch. Historical technical coverage treats audio amplifiers, SPICE models, and power-MOSFET simulation as distinct subjects rather than one universal design method; see the Electronics World article index.
Write the specification before selecting a part
Record the following values, including minimum, nominal, and maximum conditions where applicable:
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- Steady-state, RMS, and peak load current
- Switching frequency and duty-cycle range
- Load type: resistive, inductive, capacitive, motor, transformer, or converter
- Allowable overshoot, rise time, fall time, and loss
- Ambient temperature, enclosure, PCB copper, airflow, and cooling method
- Available gate-drive voltage and driver current
- Low-side, high-side, isolated, or non-isolated operation
- PCB area, package, cost, availability, and safety constraints
Load current alone cannot determine a suitable MOSFET. A high-current, high-frequency switch may need a device with higher on-resistance but much lower gate charge; a linear current limiter may need a device whose safe-operating-area (SOA) graph supports sustained dissipation.
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Understand the operating regions
Cutoff
With gate-to-source voltage below the effective turn-on requirement, drain current is nominally limited to leakage. Leakage, threshold, and capacitance still vary with temperature and voltage.
Ohmic or linear region
At sufficient gate voltage and relatively low drain-to-source voltage, the channel behaves approximately as a voltage-controlled resistor. This is the desired region for many switching intervals.
Saturation region
In the long-channel teaching model, the channel pinches near the drain and current is primarily controlled by gate overdrive. This is the region used in many common-source amplifier calculations. It is not the same as a saturated BJT switch, where “saturation” usually means a low-voltage on-state.
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For an idealized long-channel device:
ID ≈ ½ kn(VGS − VTH)²
in saturation, and
ID ≈ kn[(VGS − VTH)VDS − VDS²/2]
in the triode region. These are teaching approximations, not modern power-device predictions. Threshold voltage is measured at a small test current; it is not the gate voltage at which a power MOSFET becomes a low-resistance switch. Real parameters vary with process, current, temperature, bias, and nonlinear capacitance. Use the datasheet’s specified RDS(on) at your actual gate voltage and temperature.
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Read the datasheet as a design document
- VDS: Maximum drain-source blocking voltage under specified conditions. Select above the maximum steady-state voltage and add transient margin.
- ID: A conditional continuous-current rating, often based on an ideal case temperature or package assumption. Check PCB, case, junction temperature, and duty cycle.
- RDS(on): On-resistance at stated gate voltage and temperature. It rises with junction temperature.
- VGS(th): Threshold test point, not a usable switching-drive specification.
- QG, QGS, and QGD: Total, pre-plateau, and Miller-region gate charge at stated conditions.
- CISS, COSS, and CRSS: Input, output, and reverse-transfer capacitances that vary with voltage.
- SOA: Required for linear operation, startup, current limiting, and unclamped inductive events.
- Thermal data: Use the specified mounting conditions, transient thermal impedance, and package metrics.
- Body-diode and avalanche data: Check forward drop, reverse recovery, current, pulse conditions, and whether the rating is repetitive or a single stress limit.
Set voltage and current margins
Voltage selection
Choose VDS above the maximum bus or drain voltage, then include supply tolerance, inductive spikes, wiring and PCB inductance, ringing, and application-specific events such as load dump. Higher voltage ratings commonly trade against greater on-resistance or gate charge.
For an inductive load, stored energy is:
EL = ½ LI²
The MOSFET, clamp, snubber, freewheel path, and layout must absorb or redirect that energy. Avalanche capability is a stress limit, not permission to use uncontrolled avalanche as a normal repetitive operating mode.
Current and SOA
Use the actual RMS waveform for heating and the peak waveform for instantaneous and SOA checks. Pulsed-current ratings are meaningful only with their pulse duration and thermal conditions. A design that is safe in the fully enhanced switching state can still fail during a slow startup or current-limit event if it enters linear operation outside the SOA.
Estimate conduction, switching, and gate losses
Conduction loss
A first estimate is:
Pcond = IRMS² RDS(on) D
where D is the fraction of the relevant conduction interval. Adapt it for triangular or discontinuous current, conduction in both switch states, body-diode intervals, linear operation, and temperature-dependent resistance. In a simple always-on interval, omit D and use the RMS current for that interval.
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Include dead-time diode conduction and reverse-current paths in half bridges. The intrinsic diode is not an ideal freewheel diode: forward loss, reverse recovery, current rating, and thermal behavior can dominate.
Hard-switching loss
A rough estimate is:
Psw ≈ ½ VDSID(tr + tf)fSW
This assumes roughly linear voltage-current overlap. Actual loss depends on nonlinear capacitances, driver strength, gate resistance, Miller plateau, diode reverse recovery, commutation-loop inductance, load current, and unequal turn-on and turn-off behavior. At high frequency, a low-resistance device can lose more overall power if its charge and capacitance are large.
Gate-drive loss
Approximate required gate current with:
IG ≈ QG/tdrive
and driver-side gate power with:
Pgate ≈ QGVdrivefSW
These estimates are starting points, not substitutes for measuring the gate and drain waveforms. TI provides MOSFET loss calculators and design-support resources, including thermal and SOA material, on its CSD19536KCS support page.
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Design the gate drive
- Keep gate voltage below the absolute maximum VGS, including ringing and negative excursions.
- Confirm that a “logic-level” part specifies RDS(on) at the controller’s actual voltage.
- Use a series gate resistor to control peak driver current and ringing; too much resistance increases transition time and switching loss.
- Add a gate pulldown or pullup so reset and startup cannot leave the gate floating.
- Return the driver to the source through a short, low-inductance path; use a Kelvin-source connection where supported.
- Provide dead time in a half bridge to prevent shoot-through. Excessive dead time increases body-diode loss.
- For a high-side N-channel device, account for bootstrap, isolated, charge-pump, or floating-driver requirements. Bootstrap circuits have duty-cycle, refresh, startup, and minimum-off-time limits.
A practical gate loop is: driver output → gate resistor → MOSFET gate → source/Kelvin return → driver ground. Keep this loop separate from the high-current commutation loop.
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Thermal design
For a board-mounted device, a first estimate is:
TJ = TA + PDθJA
With a heatsink:
TJ = TA + PD(θJC + θCS + θSA)
Junction temperature, not case temperature alone, determines the critical limit. Thermal resistance depends on mounting, copper area, vias, airflow, and measurement method. Use transient thermal impedance for pulses. Because resistance rises with temperature, heating can create a feedback loop: hotter silicon increases RDS(on), which increases conduction loss. Leave margin below the absolute maximum junction temperature. TI’s MOSFET thermal resources discuss transient impedance and package metrics.
Analog MOSFET design is a different path
For an amplifier, establish the DC bias point before calculating signal gain. Common-source, common-drain, and common-gate stages use different impedance and gain relationships. Source degeneration reduces gain but improves linearity and bias robustness. A basic common-source estimate is:
Av ≈ −gm(RD ∥ ro ∥ RL)
Evaluate transconductance, output resistance, body effect, Miller capacitance, input and output impedance, noise, distortion, temperature drift, and device variation. Discrete power MOSFET small-signal behavior is not interchangeable with an integrated analog MOSFET’s process model.
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- Verify the topology with an idealized MOSFET.
- Replace it with the manufacturer’s SPICE model.
- Add realistic gate resistance, driver behavior, and supply impedance.
- Add package and PCB parasitic inductance and capacitance.
- Model the load’s actual current and voltage behavior.
- Test startup, shutdown, short circuit, current limit, and abnormal load conditions.
- Sweep temperature, bus voltage, gate resistance, load current, and device variation.
- Compare predicted gate voltage, drain voltage, current, switching time, and loss with measurements.
Vendor models are useful approximations, but may not reproduce nonlinear capacitance, reverse-recovery interaction, avalanche, linear-mode behavior, temperature-dependent parasitics, or layout-induced ringing. LTspice, TINA-TI, and PLECS are alternative simulation environments; choose one with models and system-level features appropriate to the design.
Layout and measurement preview
- Minimize the high-current switching loop and place ceramic decoupling close to the devices.
- Keep the gate loop short and separate from power-current returns.
- Use Kelvin-source routing where possible and control switch-node copper to limit capacitive coupling and EMI.
- Place snubbers and clamps at the source of ringing, not at the far end of a long trace.
- Provide adequate copper width, vias, and thermal spreading.
Measure gate-to-source voltage directly at the MOSFET pins. Use a short ground spring or differential probe; a long oscilloscope ground lead can create apparent ringing that is mostly probe-loop inductance. Low-inductance measurement is essential when evaluating switching edges, as explained in this Power Electronics News tutorial.
Common failures and recovery
If the MOSFET overheats
- Measure actual gate-to-source voltage at the pins.
- Verify that the gate reaches the voltage used for the datasheet’s RDS(on).
- Check transition time and Miller-plateau behavior.
- Separate conduction, switching, gate, diode, and dead-time losses.
- Check body-diode and reverse-recovery current paths.
- Estimate junction temperature rather than judging by case touch.
- Inspect gate-loop inductance, power-loop layout, copper area, and vias.
If it fails immediately
- Check drain-voltage overshoot and ringing.
- Check positive and negative gate-voltage excursions.
- Verify dead time and rule out shoot-through.
- Calculate inductive energy and inspect clamps or snubbers.
- Reduce bus voltage and current during debugging.
If the circuit rings
- Shorten the commutation loop and improve local decoupling.
- Tune the gate resistor.
- Add or tune an RC or RCD snubber.
- Verify the probe technique.
- Reassess output capacitance, diode recovery, and switch-node parasitics.
When another technology is a better fit
| Alternative | Possible advantage | Important limitation |
|---|---|---|
| BJT | Low-cost, low-frequency current amplification | Requires base current and has storage behavior when saturated |
| IGBT | Higher-voltage, moderate-frequency power conversion | Conduction and switching limitations at lower voltages |
| SiC MOSFET | High-voltage, high-temperature, high-frequency conversion | Demanding gate-drive, protection, and layout requirements |
| GaN transistor | Very fast, high-frequency switching | Highly sensitive layout and driver requirements |
| Integrated load switch | Protection, current limiting, reverse blocking, controlled slew rate | Less discrete optimization flexibility |
| Relay or solid-state relay | Very low switching frequency or galvanic isolation | Usually slower or less efficient for high-frequency power conversion |
| Power module | Integrated thermal, isolation, and high-power construction | Higher cost and less component-level flexibility |
A repeatable first-pass workflow
- Define voltage range, load current, frequency, duty cycle, load type, and temperature.
- Select the topology and identify every current path, including the body diode.
- Set the maximum device voltage with transient margin.
- Calculate RMS and peak current.
- Compare candidates by VDS, temperature-corrected RDS(on), QG, QGD, COSS, SOA, diode data, package, and thermal path.
- Estimate conduction, switching, gate-drive, diode, and dead-time losses.
- Estimate junction temperature with realistic mounting assumptions.
- Select the driver, gate resistor, pulldown, dead time, and high-side method if needed.
- Lay out the gate and power loops separately.
- Simulate with a vendor model and parameter sweeps.
- Prototype with current limiting and controlled voltage.
- Measure gate voltage, drain voltage, current, temperature, and ringing.
- Recalculate worst-case margins from measured waveforms.
Selection, conduction loss, switching loss, and thermal estimation are normally treated as separate design stages in switching-power references such as Switching Power Supplies A–Z. That separation prevents a favorable number in one column from hiding a failure in another.
What belongs in Part 2
A useful continuation would cover gate-driver sizing, half-bridge and high-side operation, dead-time optimization, snubber design, reverse recovery, detailed thermal validation, oscilloscope techniques, EMI, and layout optimization.
Quick Recap
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