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Microchip Updates Networking and Storage Products for AI and HPC

Microchip’s AI and HPC portfolio updates span PCIe Gen 6 switching, NVMe storage, RAID, Ethernet, power and system management. Here are the stated features and what designers should verify.
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Microchip Technology’s data-center portfolio updates span PCIe switching, NVMe controllers, RAID, Ethernet connectivity, power and system management. The changes arrive in stages: a broad connectivity and storage announcement in April 2025, PCIe Gen 6 switch and storage developments in 2025 and 2026, and a further portfolio update in October 2026. They target the movement and management of data in AI and high-performance computing (HPC) systems—not a single component that guarantees faster end-to-end performance.

What did Microchip update for AI data centers?

The portfolio combines products with distinct jobs: switches connect processors and devices; storage controllers manage NVMe drives; RAID controllers add storage-management functions; Ethernet components handle network links; and power, timing and management products support the surrounding system. Microchip’s April 28, 2025 announcement covered PCIe Gen 3, Gen 4 and Gen 5 switches, NVMe storage and RAID controllers, retimers, Ethernet PHYs, power management, system monitoring and precise timing. It said Gen 6 and Gen 7 PCIe technologies were then in development. Microchip’s April 2025 portfolio announcement describes the initial range.

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Later announcements put more detail behind the PCIe Gen 6 plans. In October 2025, Microchip introduced Switchtec Gen 6 fanout switches; in August 2026, it announced a demonstration pairing Switchtec switching with Micron 9650 NVMe SSDs; and in October 2026, it described a lower-lane-count PCIe 6.0 switch along with Flashtec controller and Adaptec SmartRAID updates. These announcements address different layers of a data-center design, so they should not be treated as interchangeable products.

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What is a PCIe Gen 6 switch used for?

A PCIe switch expands and routes connections between host processors and devices such as NVMe SSDs. In an AI or HPC server, it can help connect compute resources to multiple storage devices and support topologies that distribute storage rather than tying every drive directly to one host. Microchip describes its Switchtec Gen 6 family as a fanout switch for these kinds of systems.

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Microchip says PCIe 6.0 provides 64 GT/s per lane, twice the signaling rate of PCIe 5.0, and describes the Switchtec Gen 6 family as supporting up to 160 lanes. Those are manufacturer-stated specifications, not independent comparative benchmark results. The October 2025 announcement also lists multicast, non-transparent bridging (NTB), error containment, diagnostics and ChipLink tool support. Microchip’s Switchtec Gen 6 announcement says the family uses a 3 nm process and describes hardware root of trust and secure boot with post-quantum-safe cryptography compliant with CNSA 2.0.

How the October 2026 switch differs

The October 12, 2026 update describes a lower-lane-count Switchtec PCIe 6.0 switch with up to 64 lanes and 32 ports, plus x2, x4, x8 and x16 bifurcation options. Integrated DMA is intended to support peer-to-peer transfers while reducing host CPU involvement. Microchip also lists multicast, partitioning, hardware root of trust and secure boot for this product. These specifications describe a different scale of switch from the up-to-160-lane family announced in 2025; system designers need to match lane count, port configuration and topology to their platform.

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How does PCIe Gen 6 storage help AI and HPC?

AI training, inference and HPC jobs can involve moving large volumes of data between processors and storage. A faster interconnect can raise the available link bandwidth, while a switch can connect a host to multiple drives or support a disaggregated storage design. Actual application performance still depends on the complete system, including the processor, switch configuration, SSDs, software, workload and thermal and power limits.

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On August 4, 2026, Microchip announced a demonstration using Switchtec Gen 6 switches between host processors and multiple Micron 9650 PCIe Gen 6 NVMe SSDs. The companies framed the setup as a scalable, composable and disaggregated storage architecture for AI, HPC and cloud data centers. Microchip and Micron called the 9650 the first mass-produced PCIe Gen 6 SSD; that description is their claim, not an independently established market ranking. The announcement demonstrates a combined architecture, not an independent benchmark proving a particular application-level speedup. The Microchip–Micron demonstration announcement provides the setup details.

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Which other products were part of the portfolio updates?

The April 2025 announcement included networking, power and system-management components alongside storage products. Their roles and stated specifications differ:

Product or family Role Details stated by Microchip
800G active electrical cable (AEC) reference design Supports development of high-speed cable links. Uses the META-DX2C 800G retimer with 112G SerDes and software implementing CMIS 5.2 on a Microchip 32-bit microcontroller for QSFP-DD and OSFP AEC development.
META-DX2+ Ethernet PHY with Lambda Splitting Ethernet physical-layer connectivity for coherent-optics systems. Microchip says Lambda Splitting distributes traffic across wavelengths and can increase bandwidth efficiency by up to 50%. This is a company-stated capability, not an independently measured general result.
LAN9646 Six-port Gigabit Ethernet switch. Four integrated 10/100/1000BASE-T PHYs; SGMII, RGMII, MII and RMII interfaces; VLAN and QoS support; SPI and I²C management; Linux DSA compatibility; stated operating range of −40°C to +85°C.
MCPF1412 power module Power conversion for data-center systems. Up to 12 A output, 0.6 V to 1.8 V output from a 16 V input, in a 5.8 mm × 4.9 mm × 1.6 mm package.
dsPIC33A digital signal controllers Power-supply control and platform security functions. Presented for AI-server and data-center power control, diagnostics, firmware attestation and device authentication.
OpenBMC-related MPUs Auxiliary platform management. Intended for power shelves, enterprise storage, JBOD, cooling and chassis systems, with Redfish, out-of-band monitoring and secure-update functions described.

These details come from Microchip’s April 28, 2025 announcement. They illustrate why “AI data-center products” is a portfolio label rather than a single product category: some devices move data, while others provide power conversion, system control or Ethernet connectivity.

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What changed in Flashtec and Adaptec storage products?

Microchip’s October 2026 update also covered two storage-related product lines beyond PCIe switching:

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  • Flashtec NVMe 5016: Microchip described an enhanced PCIe Gen 5 NVMe SSD controller with CNSA 2.0 support and dual-port capability for redundant paths and load balancing.
  • Adaptec SmartRAID 4300: Announced additions include self-encrypting drive key management, RAID 6 and RAID 60, Linux/Debian/Ubuntu/Windows 11 support, dynamic NVMe configuration, persistent event logging, peer-to-peer rebuild and StorageCore API integration.

These are features described by Microchip, not independent security assessments or compatibility tests. The SmartRAID additions matter to administrators evaluating drive protection, recovery behavior and management integration; the Flashtec update is aimed at SSD-controller capabilities and path resilience. Neither replaces the need to validate a specific server, operating system, drive and software configuration. Microchip’s October 12, 2026 portfolio update lists the announced additions.

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What should buyers and system designers verify?

Choosing among these products is a system-design decision, not a simple ranking. The relevant checks depend on whether the need is PCIe switching, SSD control, RAID, Ethernet, or platform support.

  • Workload and topology: Determine the number and type of hosts and devices, required lane count, port layout, and whether the design needs direct-attached or disaggregated storage.
  • Performance evidence: Treat bandwidth figures as interface or vendor specifications, not proof of end-to-end application gains. The cited announcements do not provide independent comparative benchmark results.
  • Security and recovery: Map requirements to the specific feature: switch root of trust and secure boot, controller CNSA 2.0 support, drive encryption and key management, RAID level, redundant paths or diagnostics. A feature announcement alone does not establish system-wide security.
  • Compatibility: Check the exact switch, controller, SSD, operating-system release, management stack and server platform. The stated SmartRAID operating-system support and LAN9646 Linux DSA compatibility are product-specific.
  • Power, cooling and space: Validate system-level power and thermal constraints; the MCPF1412’s dimensions and output limits are component specifications, not a complete server power design.
  • Availability: Confirm the exact part’s sampling, production and inventory status in the relevant region with Microchip or an authorized distributor. Microchip says pricing and availability vary by device.

For the 2025 Switchtec Gen 6 family, Microchip named the PM61160-KIT evaluation kit and said switches were available for sampling to qualified customers at the time of that announcement. That dated sampling statement does not establish current inventory or general orderability.

Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.

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