Marvell Structera A 2504 is not just a conventional CXL memory expander. It is a CXL 2.0/PCIe 5.0 x16 near-memory accelerator that combines 16 Arm Neoverse V2 cores with four DDR5 memory channels. The attached memory can provide up to 4 TB of capacity and Marvell lists up to 200 GB/s of bandwidth, while the Arm cores process selected work close to that data instead of sending every operation back to the host CPU.
What Structera A is
Marvell positions Structera A as a near-memory accelerator for servers that need both more memory and computation near that memory. The device connects to a host over CXL 2.0 using a PCIe 5.0 x16 link and attaches local DDR5 through four memory channels.
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Marvell’s published configuration includes support for DDR5 speeds up to 6400 MT/s, up to two DIMMs per channel (eight DIMMs total), and as much as 4 TB of attached memory. Those are vendor specifications, not independently verified benchmark results.
Published hardware specifications
| Feature | Marvell’s stated specification |
|---|---|
| Device role | CXL near-memory accelerator |
| Host interface | CXL 2.0 over PCIe 5.0 x16 |
| Compute | 16 Arm Neoverse V2 cores at 3.2 GHz |
| Memory interface | Four DDR5 channels |
| Memory speed | Up to DDR5-6400 (6400 MT/s) |
| DIMM configuration | Up to two DIMMs per channel, eight DIMMs total |
| Maximum bandwidth | Up to 200 GB/s |
| Maximum capacity | Up to 4 TB |
The product brief describes the cores as supporting Armv9.0-A and Armv8.5-A. It also lists inline LZ4 compression and decompression, XTS-AES 256-bit encryption and decryption, an embedded hardware security module, and secure boot.
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What the 16 Arm cores do
The cores are intended to run data-processing tasks near the additional DDR5 memory. In a conventional expansion design, a host CPU issues operations against memory attached through the expansion device. A near-memory design can instead place suitable portions of a workload on the accelerator, reducing movement of data between the accelerator’s memory and the host processor.
Target workloads
Marvell specifically cites deep-learning recommendation models (DLRM), machine learning, and AI inference. These workloads can be constrained by the rate at which data is supplied to compute engines, so processing close to a high-bandwidth memory pool is the architectural rationale.
That does not guarantee a speedup for every application. Benefit depends on software support, how much of the workload can run on the Arm cores, data placement, CXL and platform configuration, and the host system’s own memory and I/O behavior. Marvell’s 200 GB/s figure is a published maximum, not an independent application benchmark.
How CXL memory expansion fits in
CXL allows a server CPU and an attached device to communicate over the PCIe physical link with memory-oriented protocols and coherency features defined by the CXL standard. A CXL memory device can add capacity that the host can address, while platform firmware and operating-system support determine how that memory is exposed and used.
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Structera A versus Structera X
Marvell’s Structera families are not interchangeable labels. Structera A is aimed at adding compute near memory; Structera X is the memory-expansion controller family for capacity-focused deployments.
| Comparison | Structera A | Structera X |
|---|---|---|
| Primary role | Near-memory acceleration plus memory expansion | Memory-capacity expansion |
| Integrated Arm compute | Yes; 16 Arm Neoverse V2 cores in the 2504 configuration | Not presented in the cited material as a near-memory compute device |
| Memory configuration | Four DDR5 channels, up to eight DIMMs, up to DDR5-6400 for Structera A 2504 | Specific comparable configuration not stated in the cited material |
| Workload emphasis | DLRM, machine learning and AI inference where bandwidth can constrain performance | High-capacity uses such as in-memory databases |
The available material does not provide a like-for-like independent benchmark, price comparison, or universal recommendation between the two families.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Platform compatibility and deployment limits
Marvell announced interoperability validation with AMD EPYC processors and fifth-generation Intel Xeon Scalable platforms. That statement identifies platform families, not blanket compatibility with every server board, firmware version, DIMM arrangement, operating system, or CXL topology. A real deployment still requires a qualified system configuration and appropriate software support.
Present-day retail availability and pricing are not established by the cited product materials. Structera A is a data-center component, so buying the chip alone does not answer the practical requirements for a working CXL server: the host platform, firmware, memory modules, cooling, and validation all matter.
Why the design matters
Adding general-purpose Arm cores to a CXL memory controller gives system designers another placement option. Instead of scaling only host CPUs or moving all data across the host link, selected memory-intensive stages could run beside the expanded memory. Compression, encryption, secure boot, and the embedded security hardware also address data movement and protection inside an enterprise accelerator.
The trade-off is software and systems complexity. Applications need a way to offload useful work to the device, and administrators need a platform that correctly enumerates, allocates, and secures CXL memory. Without that integration, the extra cores and theoretical bandwidth do not automatically translate into better application performance.
What is confirmed—and what is not
- Confirmed by Marvell’s specifications: CXL 2.0/PCIe 5.0 x16 connectivity, 16 Neoverse V2 cores, four DDR5 channels, support up to DDR5-6400, and the published 200 GB/s and 4 TB maxima.
- Confirmed by Marvell’s product positioning: near-memory acceleration for DLRM, machine learning, and AI inference, and a distinction from Structera X capacity controllers.
- Confirmed by Marvell’s interoperability announcement: validation with AMD EPYC and fifth-generation Intel Xeon platforms.
- Not established here: independent benchmark performance, universal latency reduction, current retail pricing, current availability, or compatibility with every server and DIMM combination.
The Bottom Line
Marvell Structera A 2504 is a CXL memory device with a processor attached: 16 Arm Neoverse V2 cores sit beside four DDR5 channels so selected memory-intensive work can run near up to 4 TB of expanded memory. It is therefore materially different from Structera X, which Marvell positions for capacity expansion without the same near-memory compute focus.
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