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How TSMC, Intel, and Samsung Compare as Advanced Chip Manufacturers

TSMC, Intel, and Samsung report advanced chip-production milestones, but their foundry models, process roadmaps, and packaging ecosystems differ. Here’s what the disclosures establish—and what they do not.
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TSMC, Intel, and Samsung all report advanced chip-manufacturing milestones, but they are not interchangeable suppliers—and their node names are not measurements on a common scale. TSMC is a pure-play foundry; Intel manufactures its own products while building an external foundry business; Samsung offers foundry services within a broader semiconductor company. The right comparison is therefore about business model, reported production status, design and packaging support, and the fit for a particular chip—not which company has the smallest-sounding label.

How their manufacturing businesses differ

A foundry manufactures chips designed by customers. The degree to which a manufacturer also designs and sells its own chips affects how it serves customers, what capabilities it emphasizes, and how its business is organized.

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Company Manufacturing model What its disclosures establish
TSMC Pure-play foundry TSMC says it focuses on manufacturing customers’ products. Its 2025 annual report reports 12,682 products for 534 customers across 305 technologies, indicating a broad external customer base.
Intel Integrated manufacturer building an external foundry business Intel manufactures its own products and is seeking government and commercial foundry customers. Its 2025 Form 10-K links continued development of 14A and successor leading-edge processes to securing a significant external customer for 14A.
Samsung Foundry service within Samsung Electronics’ wider semiconductor business Samsung Foundry operates alongside the company’s Memory and System LSI businesses. Its offering describes process technology, design support, manufacturing, packaging, and ecosystem partnerships.

These distinctions matter when evaluating a supplier, but they do not by themselves establish which company will offer the best schedule, yield, capacity, or commercial terms for a particular design.

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What the leading-edge production milestones say

The latest milestones in the cited company disclosures are close enough in time to invite comparison, but they are not a shared benchmark. “High-volume manufacturing” and “mass production” are each company’s status descriptions; the reports do not establish equivalent yields, volumes, customer shipments, or commercial maturity.

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Company and process Company-reported status Disclosed features or context
TSMC N2 TSMC’s 2025 annual report says high-volume manufacturing began in the fourth quarter of 2025; it expected a fast ramp in 2026. N2 is part of TSMC’s nanosheet roadmap. The report describes N2P as an N2 extension.
Intel 18A Intel’s 2025 Form 10-K says high-volume manufacturing began in late 2025. Intel says 18A introduces RibbonFET gate-all-around transistors and PowerVia backside power delivery. The filing identifies it as the company’s most advanced leading-edge node at that time.
Samsung SF2 Samsung’s current official logic-node page lists mass production starting in 2025. Samsung describes SF2 as second-generation MBCFET gate-all-around technology and lists mobile, high-performance computing (HPC), AI, and automotive applications.

These are status claims from the companies, not an independent head-to-head assessment. They show that all three report production milestones for advanced processes; they do not show that the processes have equal maturity or that one is ahead on every metric.

Why N2, 18A, and SF2 are not a direct size ranking

The labels N2, 18A, and SF2 belong to different company naming systems. They should not be read as physical dimensions measured by one common standard. A comparison based on the numeral alone cannot establish transistor density, chip area, power use, performance, yield, or cost.

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The public disclosures summarized here identify architectures and company-reported production status, but do not provide an independent, consistently defined ranking of these processes by density, yield, cost per wafer, or power-performance on a common benchmark. A defensible comparison needs a specific design and comparable results under stated conditions.

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Transistors and power delivery: the disclosed approaches

Each company describes a combination of transistor and power-delivery technologies. These features are relevant to design choices, but naming an architecture does not establish a winner without comparable results for the same workload and design constraints.

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  • Intel 18A: Intel says it combines RibbonFET gate-all-around transistors with PowerVia backside power delivery.
  • Samsung SF2: Samsung calls its transistor technology second-generation MBCFET, its gate-all-around approach.
  • TSMC: TSMC describes N2 in its nanosheet roadmap. Its later A16 process combines nanosheet transistors with Super Power Rail backside power delivery.

TSMC’s 2025 annual report scheduled N2P and A16 volume production for the second half of 2026 and A14 for 2028. Those dates are company targets stated in that report, not confirmation that a process reached volume production. The report describes A16 as suited to HPC products with complex signal routes and dense power-delivery networks. TSMC’s technology page also presents performance figures as company-stated targets relative to N2P; they should not be treated as independent test results.

Packaging and design ecosystems are part of the choice

For products that combine multiple dies, packaging and design support can matter alongside the wafer process. The companies disclose different packaging families and ecosystem offerings; availability and suitability still depend on the particular design and its requirements.

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Company Disclosed packaging and ecosystem offerings
TSMC CoWoS, InFO, and SoIC, including chip-stacking approaches.
Intel EMIB and Foveros packaging families.
Samsung Integrated 2.5D and 3D packaging, the SAFE ecosystem, and the MDI Alliance.

Samsung Foundry’s company profile describes support spanning process technology, process design kits (PDKs), design methodology, design services, manufacturing, packaging, and ecosystem partnerships. Intel’s external foundry effort and TSMC’s broad foundry customer base are also important context when assessing a prospective project. None of those descriptions guarantees a specific design’s yield, schedule, or commercial terms.

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Scale and customer breadth: what is—and is not—comparable

TSMC’s 2025 figures provide a useful picture of its own scale. They are not a three-company league table: the cited disclosures do not offer equivalent, consistently defined figures for Intel and Samsung.

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  • TSMC reported manufacturing 12,682 products for 534 customers using 305 distinct technologies in 2025.
  • It reported shipping 15.0 million 12-inch-equivalent wafers in 2025.
  • TSMC reported annual managed capacity above 17 million 12-inch-equivalent wafers at facilities managed by the company and its subsidiaries in 2025.
  • TSMC said technologies it defines as 7nm and more advanced generated 74% of its total wafer revenue in 2025.

These figures use TSMC’s own definitions and reporting. They do not establish comparable competitor capacity, leading-edge market share, yield, or cost per wafer.

Intel’s foundry outlook depends partly on external demand

Intel’s 2025 Form 10-K describes 14A as its next-generation node, in development and designed from the outset for external customers. It also warns that Intel may pause or discontinue 14A and successor leading-edge process development if it cannot secure a significant external 14A customer. That is a disclosed business risk, not evidence that 14A will fail; it does make customer adoption an important factor in evaluating Intel’s foundry plans.

How to choose a manufacturer for a real chip

There is no evidence in the cited company disclosures for a universal winner. A useful shortlist starts with the needs of the chip and the project, then asks each prospective supplier for design-specific evidence.

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  • Design fit: Identify the required performance, power, area, and integration targets, then compare process and packaging options against them.
  • Production timing: Separate processes already reported in production from future roadmap targets. Confirm the schedule and ramp assumptions for the specific process and product.
  • Capacity and execution: Ask about capacity applicable to the project, expected manufacturing milestones, and the evidence behind any yield or delivery estimates.
  • Packaging and design enablement: Check whether the required packaging, PDKs, design methodology, services, and ecosystem support are available for the design.
  • Supplier risk: Consider the manufacturer’s business model, customer commitments, and disclosed dependencies alongside technical fit.
  • Comparable evidence: Request results for the relevant design or a clearly specified benchmark. Do not substitute node names or company targets for an apples-to-apples comparison.

For a particular chip, the best choice is the supplier that can meet its design, production, packaging, schedule, and risk requirements on evidence specific to that project.

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