To multiply matrices with ARM NEON, divide the work into small vector-friendly blocks, compute each output block with Advanced SIMD operations, and add loops and address calculations around that block for a general matrix-multiplication kernel. Arm’s documented 4×4 floating-point example is a useful starting point—not a universal fastest implementation. For many projects, an optimized library or compiler auto-vectorization is the better first step; use intrinsics or assembly when measurement and control requirements justify the extra target-specific code.
Define the matrix operation before writing the kernel
For conventional matrix multiplication, A has dimensions M×K, B has dimensions K×N, and the result C has dimensions M×N. Each output element is the dot product of one row of A and one column of B:
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C[i,j] = Σ(k=0…K−1) A[i,k] × B[k,j]
Before choosing an implementation, specify the element type, how each matrix is laid out in memory, its row and column strides, and whether the result overwrites C or accumulates into existing values. These details determine how the kernel finds its data and whether its access pattern is suitable for vectorization. Arm’s teaching example is a floating-point general matrix kernel organized around 4×4 blocks.
What NEON contributes
NEON is Arm Advanced SIMD, an extension of the Arm architecture—not a separate matrix accelerator. Arm’s introductory guide covers the Armv8-A and Armv8-R profiles. In SIMD execution, one instruction applies a like operation across multiple lanes. The ACLE reference describes NEON vectors as 64-bit or 128-bit vectors containing elements of the same scalar type.
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That model makes a block kernel possible: load several values, multiply and add corresponding lanes, then store several results. The exact instructions and available operations depend on the target architecture and data type. A floating-point example should not be treated as proof that every NEON-capable processor supports every matrix-related intrinsic. The ACLE reference, for example, describes integer matrix multiplication and mixed-sign dot-product extensions introduced with Armv8.6-A; check the relevant architecture and compiler documentation for a deployment.
Start with a 4×4 block
Arm’s example computes a 4×4 region of the output from corresponding portions of A and B. Conceptually, each result in the block is formed by multiplying a row of A by a column of B and accumulating across the shared K dimension. NEON operations let the kernel perform several of those arithmetic steps in parallel, according to the chosen data arrangement and instructions.
The example keeps the columns of B in distinct variables. Arm presents this as a source-level hint that may help the compiler allocate separate registers, so work for one column can proceed while another load is waiting. It is not a guarantee: register allocation and scheduling depend on the compiler, its options, and the processor.
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Extend the block into a general matrix kernel
A general kernel wraps the block computation in loops over output tiles and calculates addresses for the corresponding regions of A, B, and C. The shared K dimension also requires a loop or equivalent accumulation across its full extent. In practice, tile sizes, strides, and tail handling must match the matrix dimensions and memory layout.
- Choose the tile and data representation. Decide the floating-point or integer type, block shape, layout, and strides. A 4×4 block is the documented teaching base; it is not automatically the best tile for a particular processor.
- Address the input regions. For each output tile, calculate the starting locations of the matching A rows and B columns using their actual strides rather than assuming a layout that the caller has not promised.
- Accumulate across K. Multiply the matching values and add them to the partial output. Preserve the intended behavior for C: initialize accumulators for overwrite semantics, or load existing values when the operation is meant to accumulate.
- Handle incomplete tiles. When M, N, or K does not fit the chosen block, use a deliberate tail path or padding strategy. Zero padding is one method described in Arm’s guide; benchmark its overhead against other approaches for the workload.
- Check the generated code and results. Confirm that the compiler emitted the intended vector operations, validate numerical behavior, and benchmark representative sizes on the target system.
Addressing and loop control are part of the kernel, not incidental details. Strides, alignment, tile edges, and the amount of work per call can all affect whether a hand-vectorized block is useful in the complete program.
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Choose the implementation route that fits the project
| Route | Control | Portability and maintenance | When it fits |
|---|---|---|---|
| Optimized library | Work through the library’s API and supported options. | Usually avoids maintaining a custom instruction-level kernel; support depends on the library and target. | Start here when a suitable library supports the operation and data types. Arm identifies the Neon-enabled Arm Compute Library as one option. |
| Compiler auto-vectorization | Express the operation in C or C++ and let the compiler attempt vectorization. | Keeps the source less tied to individual instructions, though results depend on compiler and target configuration. | Try when the code has a clear vectorizable structure and direct intrinsic control is not yet necessary. |
| NEON intrinsics | Explicitly select vector operations from C or C++. | Introduces architecture-specific code and requires attention to target support and compiler behavior. | Use when you need more control than portable source or auto-vectorization provides and can verify the generated code. |
| Assembly | Direct instruction-level control. | Requires the most architecture expertise and creates the greatest maintenance burden. | Consider only when justified by a measured need and the project can support target-specific implementation and upkeep. |
Arm identifies all four routes—library use, auto-vectorization, intrinsics, and assembly—as ways to take advantage of NEON. Their relative performance is workload- and target-dependent; the cited guide does not establish a universal winner.
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Benchmark on the target, not by assumption
Neither Arm’s overview nor its instructional matrix example supplies a universal speedup or throughput figure for this kernel. To decide whether a custom implementation helps, compare it with the library or compiler-generated baseline on the actual processor and compiler configuration. Include representative matrix sizes, layouts, strides, and tail cases; a result for one shape does not establish performance for another.
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- Inspect compiler output to confirm the intended vector instructions are present.
- Measure the complete operation, including setup, address calculations, and tail handling where applicable.
- Check numerical results against a trusted implementation using tolerances appropriate to the data type and application.
- Record the processor, compiler and options, input dimensions, and layout so the result is interpretable and repeatable.
NEON is not SME or SME2
Arm’s developer hub presents Scalable Matrix Extension (SME) as a matrix-computation extension with its own guide and examples. SME and SME2 are distinct from the NEON block-kernel approach discussed here. If the target hardware supports SME, its documentation may be relevant to that deployment, but SME material should not be mistaken for a NEON kernel tutorial.
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Official references
- Arm Neon overview and programming guidance — architecture context and implementation routes.
- Arm Neon intrinsics optimization guide — the 4×4 matrix example and its generalization.
- Arm Neon intrinsics reference — vector types and architecture-specific intrinsic information.
- Arm developer hub: Neon and SME resources — links to SIMD learning materials and SME resources.
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