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The most concrete scale disclosure in the available evidence is TSMC’s 2025 annual report. Samsung’s official foundry overview provides extensive process, ecosystem and packaging information but no comparable company-wide capacity series. Intel’s 2025 filing documents Intel 18A entering high-volume manufacturing while making later leading-edge investment partly dependent on winning a significant external customer. Those are different types of evidence, so a responsible comparison keeps them separate rather than producing an unsupported overall ranking.
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Start with the decision your chip must satisfy
A foundry comparison is useful only when it answers a manufacturing decision. Before looking at node names, write down the requirements that can disqualify a supplier:
- Product type: CPU, GPU, accelerator, networking device, memory controller, automotive part, radio-frequency device or another application.
- Targets: maximum performance, power envelope, die area, memory bandwidth, operating temperature and reliability lifetime.
- Volume and schedule: prototype quantity, qualification date, annual units and the date by which stable production is required.
- Package: conventional flip-chip, 2.5D interposer integration, chiplet assembly or 3D die stacking.
- Commercial and geographic constraints: expected wafer allocation, customer location, export-control exposure and the acceptable concentration of production in one region.
Only after those requirements are explicit should you compare process options. A mature node with proven automotive qualification may be a better fit than a newer node that is still ramping, while a chiplet design may be limited by package availability rather than transistor density.
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Use a common comparison framework
For each candidate, record the same evidence categories and date every entry. This prevents a current production result from being compared with a future announcement.
1. Production status
Classify every process as high-volume manufacturing, lower-volume or risk production, active development, facility construction, or a longer-term target. “Announced” and “in production” are not interchangeable. Ask when the statement was made and whether it covers the specific product and fab your design would use.
2. Process capability
Evaluate transistor architecture, design rules, libraries, supported voltages, SRAM behavior, density, performance-per-watt and expected yield for the actual design. Node names are vendor-specific marketing and technology labels; they do not establish equal gate pitch, metal pitch, effective density, speed, leakage or cost.
3. Scale and delivery
Separate annual capacity, wafers shipped, installed tools, booked allocation and the output available to a new customer. Always preserve the unit (such as 12-inch-equivalent wafers), year and organizational scope. A large company-wide capacity number does not guarantee an open slot on the process you need.
4. Foundry access and ecosystem
Check whether an external customer can obtain a process design kit (PDK), standard-cell and memory libraries, verified intellectual property, electronic-design-automation (EDA) flows, design services, shuttle programs, qualification support and a clear tape-out-to-production path. An internally successful process can still be impractical if external enablement is immature.
5. Advanced packaging
Match the package architecture to the system. Compare 2.5D integration, 3D stacking, chip-to-chip interconnect, thermal design, known-good-die requirements, qualification, package cost and actual capacity. Product-family names alone do not prove that a package is available for your volume or schedule.
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6. Geography and resilience
Distinguish operating fabs from announced or under-construction sites. Consider where wafers are made, where assembly and test occur, logistics to your final market, export controls and the operational impact of a regional disruption.
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Put each future node and facility on a dated timeline. Record dependencies such as customer commitments, construction completion, capital approval, equipment installation and qualification. A conditional roadmap should never be counted as current capability.
What the published evidence shows at a glance
| Comparison area | TSMC | Samsung Foundry | Intel |
|---|---|---|---|
| Current process evidence | 2025 report covers a broad portfolio; 7nm-and-beyond technologies generated 74% of total wafer revenue in 2025 (company-reported). | Official overview describes mass production from legacy through advanced processes, including 3nm GAA, but does not provide a comparable production-volume series. | Intel 7, Intel 4 and Intel 3 reported in production; Intel 18A entered high-volume manufacturing in late 2025 (company-reported). |
| Public scale figures | 15.0 million 12-inch-equivalent wafers shipped and more than 17 million 12-inch-equivalent wafers of annual capacity in 2025; 305 process technologies, 12,682 products and 534 customers. | No company-wide wafer-capacity, shipment or customer-count figures in the reviewed official page. | The 2025 filing does not provide a directly comparable foundry capacity and customer series for the leading-edge nodes. |
| External-customer orientation | Dedicated foundry model serving HPC, smartphones, IoT, automotive and consumer electronics. | SAFE ecosystem covers IP, EDA, cloud, design services, OSAT partners and packaging support. | Intel says it is seeking to establish Intel 18A as its first significant foundry node for government and commercial customers. |
| Advanced packaging evidence | CoWoS, InFO, TSMC-SoIC and COUPE are identified as packaging or stacking technologies. | MDI Alliance offers a turnkey approach for heterogeneous 2.5D and 3D packaging. | EMIB has been in high-volume manufacturing since 2017; EMIB-T was introduced in 2025. Foveros provides 3D die stacking. |
| Important roadmap condition | A14 development is progressing, with volume production scheduled for 2028; this is a plan, not current output. | SF2Z, SF2A and 1.4nm GAA are described as development or future plans; the page does not establish volume, yield or allocation. | Intel 14A and successor leading-edge development may be paused or discontinued without a significant external customer. |
These entries come from company-published material and are not an independent head-to-head audit. The figures cannot be used to infer equivalent yield, wafer price, performance or customer allocation.
TSMC: the clearest disclosed scale, with allocation still requiring confirmation
TSMC describes itself as a dedicated foundry serving high-performance computing, smartphones, the Internet of Things, automotive and consumer electronics. In its 2025 annual report, it says it manufactured 12,682 products for 534 customers using 305 distinct process technologies. It reports 15.0 million 12-inch-equivalent wafer shipments and annual manufacturing capacity of more than 17 million 12-inch-equivalent wafers in 2025. Shipments are output delivered during the year; capacity is the stated annual manufacturing capability. Neither number is the amount available to your project.
TSMC also reports that technologies at 7 nanometers and beyond represented 74% of total wafer revenue in 2025. This is a revenue mix, not a percentage of wafers, installed tools or available leading-edge allocation. Treat all of these numbers as TSMC’s company-reported figures rather than independently comparable statistics for Samsung or Intel.
Footprint and timing
The 2025 report lists facilities in Taiwan, China, Japan and the United States, plus a specialty-technology fab under construction in Dresden, Germany. TSMC Arizona’s first facility began volume production of 4nm in the fourth quarter of 2024. The second Arizona facility was installing systems and targeted high-volume production in the second half of 2027; construction on a third began in 2025. Japan’s first Kumamoto fab began volume production at the end of 2024, while a second was under construction. Dresden is planned for 28/22nm planar CMOS and 16/12nm FinFET.
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These dates describe a mix of operating fabs, construction and targets. If your design requires a particular country of manufacture, ask TSMC which fab, process variant and qualification status apply instead of treating the entire network as interchangeable.
Packaging choices
TSMC identifies CoWoS, InFO, TSMC-SoIC and COUPE as advanced packaging or chip-stacking technologies. Select among them by the system architecture: for example, whether the design needs a large 2.5D integration footprint, fine-pitch chip-to-chip connections or 3D stacking. Confirm package capacity, substrate and interposer availability, thermal limits, qualification and cost in the commercial proposal.
Roadmap boundary
TSMC says A14 development is progressing and volume production is scheduled for 2028. That statement is a future plan, not evidence that A14 is currently available for tape-out or volume orders.
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Samsung Foundry: broad ecosystem and roadmap, fewer public scale numbers
Samsung’s official foundry overview describes a manufacturing network spanning Giheung, Hwaseong and Pyeongtaek in Korea, and Austin and Taylor in the United States. It presents mass-production capability for legacy and advanced semiconductors and identifies 3nm gate-all-around (GAA) as a technology achievement. It also says 4nm FinFET will continue to serve mobile and automotive applications.
The same page describes SF2Z, a 2nm process with backside power delivery for high-performance computing and artificial-intelligence applications, and SF2A for automotive as development plans. It also describes 1.4nm GAA as future development. None of those roadmap labels, by themselves, establishes high-volume status, yield, capacity, customer allocation or production date.
Customer enablement
Samsung describes a design platform that includes libraries, PDKs, design methodology, IP, design support, packaging and cloud services. Its SAFE ecosystem includes IP, EDA, cloud, design-service and OSAT partners. For complex multi-die systems, the MDI Alliance is presented as a turnkey offering for heterogeneous 2.5D and 3D packaging.
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For procurement, convert those descriptions into checkable deliverables: the PDK release that supports your design rules, qualified third-party IP, EDA-version compatibility, design-service scope, package assembly site, qualification plan and committed production window. The reviewed company page does not publish a company-wide wafer-capacity figure, customer count or standardized yield series comparable to TSMC’s 2025 disclosures. Do not fill those gaps with estimates unless they come from a separately identified, dated source.
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Intel: 18A production and established packaging, with a customer-dependent later roadmap
Intel’s fiscal 2025 annual report states that Intel 7, Intel 4 and Intel 3 were in production. It identifies Intel 18A as the company’s most advanced leading-edge node and says it entered high-volume manufacturing in late 2025. Intel describes RibbonFET as its gate-all-around transistor implementation and PowerVia as its backside-power-delivery implementation. These are Intel’s technology claims; without a common benchmark, they do not prove that 18A is faster, denser or cheaper than a competitor’s similarly named node.
Intel’s filing states: We are seeking to establish Intel 18A as our first significant foundry node for government and commercial customers.
The sentence documents an external-foundry ambition, not a guaranteed allocation or an independently measured market share.
14A and the commercial dependency
Intel says Intel 14A is under active development and may incorporate high-numerical-aperture extreme ultraviolet lithography in high-volume logic manufacturing. The filing also says Intel is seeking a significant external customer and may pause or discontinue Intel 14A and successor leading-edge development if it cannot secure one. Therefore, 14A belongs in a risk register as a conditional roadmap item, not in a list of currently available nodes.
Manufacturing and assembly footprint
Intel identifies key 2025 production fabs in Oregon, Arizona, Ireland and Israel. Key assembly and test sites were in China, New Mexico, Vietnam and Malaysia, with New Mexico identified as a key advanced-packaging location. The filing says Ohio fab construction was slowed and planned expansions in Germany and Poland were discontinued. This is a dated fiscal-2025 snapshot; confirm current schedules and customer-specific routing during contracting.
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Intel says EMIB has been in high-volume manufacturing since 2017, making it a mature 2.5D integration option in the company’s portfolio. Intel introduced EMIB-T in 2025 and expects adoption to scale beginning in 2026. Foveros is Intel’s 3D die-stacking family, with variants whose future production timing remains a plan. For a chiplet product, ask which EMIB or Foveros variant, die size, interconnect pitch, thermal design, known-good-die flow and package volume are covered by the quote.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to compare process nodes without being misled
Do not equate the labels
“3nm,” “2nm,” “18A” and similar terms are not a universal ruler. One vendor’s label may emphasize a generation name, while another’s reflects a different combination of gate pitch, metal pitch, transistor architecture and power-delivery technology. Ask for the metrics that affect your design: effective logic density, performance at a stated voltage, leakage, SRAM density, supported analog or high-voltage devices, design-rule restrictions and expected yield range.
Separate company claims from neutral measurements
The available material does not establish a common, independently measured yield, wafer-price, performance, cost or node-equivalence dataset. Treat vendor benchmarks as useful for understanding what the vendor claims, then request comparable models, test-chip data and contractual quality commitments for the specific process option.
Check the exact process variant
A base node can have variants optimized for mobile, high-performance computing, automotive reliability, radio frequency or backside power delivery. The variant determines libraries, design rules, voltage options, qualification and schedule. Comparing only the headline node can select the wrong process even within the same foundry.
How to compare capacity and delivery
Use a capacity worksheet with separate fields for annual installed capacity, current utilization, committed customer allocation, your requested wafer start rate, geographic source and ramp date. TSMC’s 15.0 million shipments and more than 17 million capacity figures illustrate why the distinction matters: shipped wafers and theoretical annual capacity answer different questions. Samsung’s reviewed page and Intel’s filing do not provide equivalent public totals, so a fair procurement comparison requires direct quotations and commitments from each supplier.
Request a written answer to these questions:
- Which fab and process variant will manufacture the wafer?
- What is the earliest engineering-wafer date and the first date for qualified volume?
- What wafer-start rate is reserved after qualification, and for how long?
- Which steps are constrained: lithography, specialty modules, substrates, interposers, assembly or test?
- Where will wafers, packages and tested units be produced, and what alternate routing exists?
- What happens if demand exceeds the forecast or the ramp slips?
How to compare advanced packaging
Packaging can determine system performance and supply more than the front-end node. Start with the architecture your product actually needs:
- 2.5D integration: multiple dies connected on an interposer or comparable high-density substrate; evaluate interposer size, routing, memory integration, substrate supply and thermal limits.
- 3D stacking: vertically connected dies; evaluate bonding method, alignment, test coverage, heat removal, repairability and known-good-die requirements.
- Chiplet integration: combine dies from possibly different process generations; evaluate die-to-die protocol, package escape routing, test partitioning and yield economics.
TSMC’s CoWoS, InFO, TSMC-SoIC and COUPE; Samsung’s MDI Alliance; and Intel’s EMIB and Foveros are technology families, not a neutral ranking. Compare package drawings, electrical limits, qualification standards, capacity by quarter, assembly location, non-recurring engineering cost and recurring package cost for your design.
A practical selection process
- Freeze requirements: document performance, power, die size, process options, package, annual volume, qualification markets and required production date.
- Shortlist viable process variants: include only nodes and specialty options whose stated status matches your schedule; exclude roadmap-only items from the committed plan.
- Audit enablement: obtain the PDK, libraries, IP list, EDA support matrix, design-rule manual and a named design-service contact.
- Validate with a test vehicle: use a shuttle or prototype to measure the design’s speed, leakage, SRAM behavior, thermal performance and package interactions.
- Verify manufacturing allocation: get fab, wafer-start, qualification and package-capacity commitments in writing, with remedies for missed milestones.
- Model total delivered cost: include masks, wafers, yield loss, test, substrate or interposer, assembly, logistics, inventory and the cost of a second source.
- Score resilience and roadmap risk: record geographic concentration, export-control exposure, construction dependencies and customer conditions such as Intel’s stated requirement for a significant external customer for 14A continuation.
- Make a schedule-gated decision: select a primary source only when its process, package and capacity are all qualified; maintain a fallback design or process where the business case justifies it.
Common comparison mistakes
- Ranking node numbers: labels are not proof of equivalent density or performance.
- Calling a roadmap production: A14, SF2Z, SF2A, 1.4nm GAA and similar entries require dates and status labels.
- Treating capacity as allocation: company-wide capacity does not guarantee your wafer starts.
- Mixing evidence types: a customer count, a process announcement and a package launch measure different things.
- Ignoring packaging: an advanced logic wafer is not useful if the required interposer, substrate or assembly flow is unavailable.
- Assuming geographic equivalence: a planned fab is not current output, and a regional move can change qualification and logistics.
- Using unsupported peer estimates: the available sources do not establish comparable neutral yield, price or node-equivalence figures.
What a defensible conclusion looks like
Choose TSMC when the design benefits from a dedicated-foundry model and the supplier can confirm the required process, allocation and package route; its 2025 report provides the most detailed public scale evidence here, but that evidence does not itself reserve capacity. Choose Samsung when its specific process, design ecosystem and 2.5D/3D packaging route meet the design and the commercial team can substantiate schedule, yield and allocation beyond the roadmap descriptions. Choose Intel when Intel 18A or an established Intel packaging flow fits the product and Intel can provide the external-foundry commitments your program needs; treat Intel 14A and later nodes as conditional until the customer and investment dependencies are resolved.
The correct output of the comparison is therefore a dated, process-specific sourcing decision with documented assumptions—not a permanent league table of TSMC, Samsung and Intel.
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