Choose a foundry by matching your chip’s workload, process, package, and delivery needs—not by picking the smallest node name or the best-known supplier. For an AI accelerator, HBM and advanced packaging may matter as much as the wafer process. For a robotics chip, compute is only part of the brief: sensor and actuator interfaces, memory, power, thermal limits, reliability, and production volume can make a mature process the better fit.
Use a shortlist to test technical fit, design enablement, manufacturing evidence, commercial terms, and supply-chain constraints. Public capability descriptions can identify options; only a project-specific proposal and technical diligence can establish whether a foundry can meet your requirements.
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1. Translate the product into manufacturing requirements
Before approaching foundries, document what the chip must do and the conditions under which it must do it. Separate hard requirements from targets that could move if they drive disproportionate cost, schedule risk, or design complexity.
Build a design brief
- Workload: target throughput and latency, including the workloads and operating modes that matter most.
- Power and thermal envelope: expected power, cooling assumptions, and permitted operating temperatures.
- Physical design: target die area, package dimensions, board constraints, and I/O requirements.
- Memory and bandwidth: capacity, bandwidth, and whether the design depends on HBM or other memory interfaces.
- Interfaces and specialty needs: for robotics, list actual sensor, actuator, and communications interfaces; also identify analog, mixed-signal, nonvolatile-memory, or high-voltage requirements.
- Reliability: required qualification and operating life, plus the real deployment environment, such as an industrial setting or a vehicle.
- Volume and timing: forecast unit volumes by year, desired first-silicon date, and production launch date.
These details prevent a common mismatch: selecting a process for peak compute performance when the product is constrained by I/O, power, specialty features, packaging, or cost instead.
#1 Best Overall
- Tang Mega 138K Pro Dock development board kit uses GW5AST FPGA as the main controller chip, the chip has 138240 LUTs and REGs, and a series of resources such as 12 PLLs to meet a variety of functional requirements, integrated 800MHz RISC-V hardcore processor, and BTB connectors to connect with the backplane.
- The Tang Mega 138K Pro Dock single board computer is equipped with Gigabit Ethernet, SFP+ and PCle interfaces, which are suitable for learning and verifying high speed FPGA communication. It is also equipped with multiple camera interfaces and display interfaces, which can be easily used for image acquisition and display.
- Tang Mega 138K Pro Dock single board computer on board rich peripheral interfaces, hard-core compatible with PCle 3.0 external lead x4 interface, a single transmission rate of up to 8GT / s (GT = Gigabyte Transfers), through the PCle x4 interface can realize up to 32GT / s high-speed data transfer. The core board measures 50mm x 70mm.
- Tang Mega 138K Pro Dock development board can be connected to the standard SFP/SFP + fiber optic transceivers, each way the transmission rate of up to 10Gbps, so that FPGAs can also use high-speed fiber optic communication for stable and reliable, suitable for high-speed communications, protocol conversion, high-performance computing and other occasions.
- Provide core board package, customers can customize the design of the base board, not only can learn to customize the core board features, but also to facilitate industrial customers to directly embed the existing program to bring more diverse learning experience, more convenient development and integration.
2. Choose a process family, not a node slogan
Ask which available processes can meet the design’s performance, power, area, reliability, specialty-feature, and cost requirements. A mature process may be the stronger option when the chip needs analog or high-voltage features, lower cost, or less process risk. A leading-edge process may be justified when density or performance gains outweigh its design demands and cost.
Compare evidence that matters to your design
Node names are vendor-defined labels, not direct measurements of physical feature size or a reliable cross-vendor performance ranking. Request the process design kit (PDK), applicable design rules, and design-relevant performance evidence under the foundry’s access terms. Confirm whether the process is in production and suitable for your schedule; a roadmap announcement alone does not establish production availability.
Any process performance figure should be read as a claim about the specific process and comparison named by its vendor. For example, TSMC says A16, compared with N2P, offers 8–10% speed improvement at the same Vdd, 15–20% lower power at the same speed, and up to 1.10× chip density. Those are TSMC’s stated comparisons for those processes, not an independent benchmark or a general comparison across foundries. Ask for evidence using assumptions and workloads relevant to your design.
Rank #2
- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
3. Verify that the design ecosystem is ready
A process is not usable for your project merely because it exists. Your team needs access to the right PDK, qualified tools, design rules, IP, signoff flows, and engineering support. Gaps in these areas can threaten feasibility or schedule even when the process appears to meet headline specifications.
Check these items with each candidate
- PDK access, version, design rules, and applicable access terms.
- Qualified EDA tool versions and flows for design-rule checking (DRC), layout-versus-schematic checking (LVS), parasitic extraction, and signoff.
- Availability and qualification status of required memory, interface, and other IP blocks.
- Reference flows, design reviews, application engineering, and escalation contacts.
- Whether shuttle or prototyping options are available and suitable for the project.
TSMC describes its Open Innovation Platform as providing design enablement and EDA certification. Samsung describes SAFE partner design enablement for HPC and AI. These descriptions establish that the ecosystems exist; they do not confirm that a particular customer has access to a qualified flow or to the IP it needs.
4. Treat packaging, memory, and test as part of the chip choice
For designs using HBM, chiplets, high-speed die-to-die links, or large compute dies, the package can be a first-order design constraint. Evaluate the wafer process and package together rather than choosing one first and assuming the other will follow.
Rank #3
- Designed for students and beginners looking to understand Digital Logic, fundamentals of FPGAs
- Features the Xilinx Artix 7 FPGA compatible with Vivado Design Suite WebPACK Edition (free download available from Xilinx)
- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
- Expansion opportunities with four Pmod ports including 3 standard 12-pin Pmod ports and 1 dual
- Does NOT ship with micro USB cable
Questions for an HBM or chiplet design
- Which package architectures and HBM configurations are supported for the proposed process and design?
- What are the limits and design rules for interposers, bridges, die-to-die connections, and package dimensions?
- Which assembly and test flows are available, and what known-good-die strategy is expected?
- What design guidance is available for thermal management and power delivery?
- Which package-design tools and engineering support are available?
- What capacity, schedule, and allocation terms can be committed for the required package?
TSMC describes CoWoS as 2.5D packaging for HPC and AI and says it is expanding capacity. Samsung describes heterogeneous integration, including logic and HBM, and 2.5D configurations it identifies as production-qualified. These are vendor capability statements, not confirmation of project access, allocation, price, schedule, or yield.
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5. Compare foundries on evidence, not broad claims
Ask each candidate to substantiate its proposed process and package for your design. Look for evidence relevant to the required qualification, production plan, and operating environment; do not treat a general marketing statement as a substitute for project-specific diligence.
Build a common comparison
| Decision area | What to compare | Evidence to request |
|---|---|---|
| Process and design fit | Workload-relevant PPA, specialty features, PDK readiness, and required IP. | Applicable design rules, tool and IP qualification status, and performance evidence tied to your assumptions. |
| Package and memory | HBM support, interposer or bridge options, die-to-die links, test, thermal design, and power delivery. | Supported configurations, design constraints, engineering guidance, and capacity terms. |
| Manufacturing maturity | Relevant qualification, production experience, yield learning, process control, and failure handling. | Qualification status, yield-ramp assumptions, change-notification policy, quality systems, and failure-analysis process. |
| Commercial terms | Total good packaged-chip cost, NRE, minimum volumes, capacity, lead time, and flexibility. | Comparable written quotes and contract terms based on the same design and volume assumptions. |
| Location and resilience | Jurisdictions, dependencies, logistics, and customer or program requirements. | Locations and dependencies across fabrication, substrate and HBM supply, assembly and test, and delivery. |
| Engineering relationship | Access to application engineers, design reviews, response expectations, and escalation. | Named points of contact, support scope, and agreed escalation path. |
TSMC describes manufacturing controls spanning front-end and back-end stages. Intel Foundry’s fact sheet describes a full-stack process and packaging offer and makes scale claims. Treat these as company descriptions, not independent rankings or proof of performance on your project. Request evidence for the specific process, package, and manufacturing plan under consideration.
Rank #4
- The best way to get started with FPGAs: Using a simple board with projects that build on eachother, now anyone can get started with FPGA development!
- Fun peripherals available: With 4 LEDs, 4 push-buttons, 7-segment display, USB connector, a VGA connector, and a PMOD (for expansion) you can have dozens of fun projects available to you out of the box!
- Works with Verilog and VHDL: No matter which programming language you want to get started with, the Go Board will work for you!
- No extra device required: Simply plug the Go Board into a USB port and go! Getting started with FPGAs has never been easier.
- Works with all operating systems: Windows, Mac, Linux
6. Compare complete project economics
Public technology pages do not establish which foundry will be cheapest or fastest for your chip. Obtain written proposals built on identical assumptions so apparent price or schedule differences are meaningful.
Make quotes comparable
- Engineering, mask, and other non-recurring engineering (NRE) charges, including payment timing.
- Wafer price and wafer size, plus assumptions for gross die and tested die yield.
- Package, assembly, and test costs, with the assumed package configuration.
- Minimum volumes, capacity reservation, lead time, and any volume commitments.
- Cancellation, rescheduling, and capacity-change terms.
- IP, confidentiality, logistics, and currency terms.
Model the expected cost per good packaged chip at realistic volumes. Run sensitivity cases for yield, schedule, and volume: a quote that looks favorable at a nominal yield or forecast may not remain favorable if the ramp is slower or demand changes. Keep each foundry’s assumptions visible so the comparison does not conceal differences in scope.
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7. Check geography, resilience, and obligations early
Map the complete supply chain: wafer fabrication, substrates and HBM, assembly and test, shipping routes, and customer location. Check procurement rules, government-program conditions, export controls, security needs, and destination requirements with qualified counsel and the relevant foundries. The applicable answer depends on the chip, counterparties, and destination; broad U.S. semiconductor supply-chain context does not determine any one company’s legal obligations.
Best Value
- [FPGA RISCV CPU] Tang Primer 25K Dock single board computer is a new generation of modular development board with onboard RISC-V soft core, 23K LUT4 FPGA GW5A RISCV CPU, supports MIPI 2.5Gbps Ethernet, and is equipped with a USB-JTAG debugger , 3x PMOD interface, 1x USB interface and 1x 40P pin header interface to facilitate FPGA programming.
- [PMOD Interface Module] The Tang Primer 25K Dock single board computer supports using the PMOD interface to connect simple modules such as HDMI modules, game controller modules and LED modules. It can also use the 40 PIN GPIO interface to connect SDRAM modules, dual DVP camera modules and other more complex functions. module.
- [Small Size, High integration] Tang Primer 25K Dock single board computer is a small, highly integrated FPGA development board. It only needs to provide a 5V power supply to the core board and correctly set the configuration pins. It can be applied to any space with limited space. scene.
- [Rich Peripheral Pins] Tang Primer 25K Dock development board integrates Gowin GW5A-LV25MG121, 64Mbit SPl FLASH, DC-DC power supply and BTB connector. Its core board leads to 76 GPIOs and 1 hard core 4lane MIPI line and 3 power outputs for users to use.
- [Application Scenarios] The Tang Primer 25K Dock development kit is equipped with a downloader and does not need to be connected to other downloaders for programming, making secondary development and programming easier. It can be widely used in FPGA education and teaching, game equipment, cameras, and security monitoring equipment wait
8. Build a shortlist and run diligence
Compare at least two credible candidates using the same design brief, technical questions, and commercial assumptions. A useful shortlist is not a ranking of node names: it is a set of options that each appear technically plausible and can provide enough evidence to evaluate schedule, cost, and risk.
- Send the same requirements brief. Include workload, PPA targets, die size, interfaces, package and memory needs, reliability, volume by year, and dates.
- Request process and ecosystem details. Ask which processes are in production for your schedule and which PDK, EDA versions, IP, and signoff flows are available and qualified for your design.
- Request package and capacity details. For HBM or chiplet designs, ask for supported configurations, package engineering support, capacity, and the terms under which it can be committed.
- Request manufacturing evidence. Ask what supports the proposed qualification, yield assumptions, and ramp schedule; how process changes are notified; and how failures are analyzed and escalated.
- Request like-for-like commercial proposals. Compare NRE, masks, wafers, packaging, test, yield assumptions, minimum volumes, reserved capacity, and contract flexibility on the same basis.
- Resolve supply-chain constraints. Confirm relevant locations, dependencies, customer or program rules, and any legal questions with qualified advisers before committing.
Advance a candidate only when its technical fit, design enablement, package path, manufacturing plan, commercial proposal, and supply-chain arrangement all have evidence appropriate to your project. The strongest public capability page is not a substitute for those commitments.
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