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How to Build and Test Embedded AI Applications with AMD Tools

A practical guide to choosing an AMD adaptive-SoC path, preparing and integrating an AI model, testing in QEMU, and validating on a target board.
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For embedded inference on AMD adaptive SoCs, start by matching the board family to the current Vitis AI support matrix, then build and test in stages: prepare and compile the model, integrate the application, run the documented QEMU hardware-emulation flow, and validate the complete workload on the target board. Vitis AI is a toolchain within a broader Vitis embedded development flow—not a single compiler command. Ryzen AI Software is a separate PC deployment path, not the board-level adaptive-SoC workflow.

Choose the AMD device and software path first

AMD’s Vitis AI Developer Hub currently lists General Access support for Versal AI Edge and Versal AI Edge Series Gen 2. Its reference-kit mapping names VEK280 for Versal AI Edge and VEK385 for Versal AI Edge Gen 2. Confirm the supported-device matrix and release-specific instructions before choosing a board: support and mappings can change, and not every AMD FPGA or adaptive SoC follows the same current flow.

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For Versal AI Core and Zynq UltraScale+ MPSoC with NPU technology, AMD directs developers to contact an AMD representative for support information; the hub also links legacy DPU documentation. Do not assume that the current General Access flow applies to these devices.

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AMD’s Vitis 2026.1 tutorial material covers a broader board matrix—VCK190, VEK280, VEK385, and VRK160, with their respective AI Engine architectures. That tutorial coverage does not mean every board has the same Vitis AI status or model-deployment path. Select the tutorial and platform artifacts for the exact device and release you intend to use.

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Write down the workload before selecting a kit

AMD’s public pages establish supported families and example use cases, but they do not choose a board for a particular workload. Record the model and framework, input shape, precision, latency and throughput goals, power and memory limits, operating environment, and whether the application needs video or another streaming interface. These requirements shape both board selection and the tests needed to establish that the application meets its goals.

Understand what Vitis AI and Vitis each do

Vitis AI combines components used to deploy inference, including compiler tooling, NPU IP, runtime software, libraries, and utilities such as the Quark quantizer. AMD describes a flow that supports mainstream deep-learning frameworks, CNNs and select vision transformers, model quantization, compilation, and runtime APIs. The exact compatible model operators and deployment steps depend on the target and release, so follow the platform-specific documentation rather than treating those capabilities as universal guarantees.

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The wider Vitis embedded flow handles platform and application development around the inference workload. AMD’s UG1400 Vitis Unified Software Platform documentation, version 2026.1, covers embedded software development, platform and application creation, builds, debugging, and IDE functions. In an integrated application, make explicit which work runs on the CPU, programmable logic, and the AI engine or NPU, how data moves between them, and which runtime dependencies must be present on the target.

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Install a release-matched development environment

Use the Vitis, Vitis AI, base-platform, and board-artifact versions specified for the chosen device. AMD’s cited Vitis tutorial is for Vitis 2026.1 and Vivado 2026.1, released July 20, 2026. It calls for the corresponding base platform, matching EDF Yocto SDK and root filesystem, and board-appropriate QEMU prebuilts. The tutorial also instructs users to set PLATFORM_REPO_PATHS. Treat these as tutorial-specific requirements: check the current instructions for your board and release instead of mixing artifacts from different versions.

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AMD’s Vitis 2026.1 embedded-software documentation is identified as UG1400 and was released September 25, 2026. Use the documentation version that matches your installed tools; UI labels and supported platform details may differ between releases.

Prepare and compile the model

Check model compatibility

Begin with a model path supported for the target toolchain and verify its framework, operators, tensor shapes, and precision requirements against the relevant Vitis AI documentation. Plan how the model’s inputs and outputs connect to preprocessing, postprocessing, and the rest of the embedded application. An isolated model that compiles is not yet a working product if its interfaces or data movement do not fit the system.

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Evaluate quantization with the real task

Quantization can change the balance among accuracy, performance, power, and memory. AMD’s tools are intended to help manage these trade-offs, but the cited material does not establish a general speedup or accuracy result that applies across models and boards. Compare task accuracy before and after quantization, then measure latency, throughput, power, and memory for the intended workload on the target. Keep the evaluation data, quantization settings, and model artifact version with the results.

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Compile and integrate for the platform

Follow the compiler and runtime instructions for the selected platform, then build the surrounding embedded application. AMD’s Vitis 2026.1 tutorial demonstrates building AI Engine and HLS kernels, compiling a host application, and running it in emulation and on a board. Use the target-specific project configuration and make the division of work, interfaces, transfers, and runtime dependencies explicit. Do not carry an artifact or build setting from a different platform or release without confirming compatibility.

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Test in emulation, then validate on the board

Run the documented QEMU hardware-emulation stage

The Vitis 2026.1 tutorial’s test sequence includes running the built application in QEMU hardware emulation before board execution. Use repeatable input fixtures and capture logs, expected outputs, and error cases so a failure can be reproduced. Emulation helps exercise the documented build and application flow, but it is not proof of every physical-board behavior; do not infer unrepresented peripheral, timing, or sustained-operation behavior from a successful emulation run.

Measure the complete workload on target hardware

Run the same representative inputs on the chosen evaluation board and assess the whole application, not only the inference kernel. Include preprocessing, transfers, postprocessing, sustained operation, memory use, and recovery from invalid inputs. Where relevant, observe power and thermal conditions under the intended operating environment. These are validation checks for your system, not performance results reported by AMD’s cited documentation.

Keep the test inputs and application configuration consistent between emulation and the board where possible, then investigate differences at the interfaces and runtime boundaries. Record end-to-end latency and throughput under defined conditions; neither a tool’s supported model range nor a successful build establishes how fast a particular workload will run.

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Keep the deployment reproducible

For each validated build, preserve the board model and revision, firmware and software releases, compiler and runtime versions, model artifact, quantization settings, build flags, and validation data. Recheck AMD’s support matrix and compatibility notes whenever the device, toolchain, model, or runtime changes. This record makes it possible to distinguish a model change from a platform or software change when results differ.

How Ryzen AI Software differs

Ryzen AI Software is related to Vitis AI but targets Ryzen AI PCs, where supported inference can use the NPU and/or integrated GPU. AMD’s Ryzen AI Software 1.8.0 documentation, updated September 28, 2026, describes a PC workflow using ONNX Runtime and the Vitis AI Execution Provider; models trained in PyTorch or TensorFlow may be deployed through that route. This PC flow is not a substitute for selecting a supported adaptive-SoC board, matching its platform artifacts, and validating the embedded application on that board.

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